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8ca8ac1024
Some registers for the Exynos 4412 ISP (Camera subsystem) clocks are located in the ISP power domain. Because those registers are also located in a different memory region than the main clock controller, support for them can be provided by a separate clock controller. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
311 lines
9.0 KiB
C
311 lines
9.0 KiB
C
/*
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* Copyright (c) 2013 Samsung Electronics Co., Ltd.
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* Author: Andrzej Hajda <a.hajda@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Device Tree binding constants for Exynos4 clock controller.
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*/
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#ifndef _DT_BINDINGS_CLOCK_EXYNOS_4_H
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#define _DT_BINDINGS_CLOCK_EXYNOS_4_H
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/* core clocks */
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#define CLK_XXTI 1
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#define CLK_XUSBXTI 2
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#define CLK_FIN_PLL 3
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#define CLK_FOUT_APLL 4
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#define CLK_FOUT_MPLL 5
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#define CLK_FOUT_EPLL 6
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#define CLK_FOUT_VPLL 7
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#define CLK_SCLK_APLL 8
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#define CLK_SCLK_MPLL 9
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#define CLK_SCLK_EPLL 10
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#define CLK_SCLK_VPLL 11
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#define CLK_ARM_CLK 12
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#define CLK_ACLK200 13
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#define CLK_ACLK100 14
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#define CLK_ACLK160 15
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#define CLK_ACLK133 16
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#define CLK_MOUT_MPLL_USER_T 17 /* Exynos4x12 only */
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#define CLK_MOUT_MPLL_USER_C 18 /* Exynos4x12 only */
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#define CLK_MOUT_CORE 19
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#define CLK_MOUT_APLL 20
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#define CLK_SCLK_HDMIPHY 22
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#define CLK_OUT_DMC 23
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#define CLK_OUT_TOP 24
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#define CLK_OUT_LEFTBUS 25
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#define CLK_OUT_RIGHTBUS 26
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#define CLK_OUT_CPU 27
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/* gate for special clocks (sclk) */
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#define CLK_SCLK_FIMC0 128
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#define CLK_SCLK_FIMC1 129
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#define CLK_SCLK_FIMC2 130
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#define CLK_SCLK_FIMC3 131
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#define CLK_SCLK_CAM0 132
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#define CLK_SCLK_CAM1 133
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#define CLK_SCLK_CSIS0 134
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#define CLK_SCLK_CSIS1 135
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#define CLK_SCLK_HDMI 136
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#define CLK_SCLK_MIXER 137
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#define CLK_SCLK_DAC 138
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#define CLK_SCLK_PIXEL 139
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#define CLK_SCLK_FIMD0 140
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#define CLK_SCLK_MDNIE0 141 /* Exynos4412 only */
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#define CLK_SCLK_MDNIE_PWM0 142
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#define CLK_SCLK_MIPI0 143
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#define CLK_SCLK_AUDIO0 144
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#define CLK_SCLK_MMC0 145
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#define CLK_SCLK_MMC1 146
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#define CLK_SCLK_MMC2 147
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#define CLK_SCLK_MMC3 148
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#define CLK_SCLK_MMC4 149
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#define CLK_SCLK_SATA 150 /* Exynos4210 only */
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#define CLK_SCLK_UART0 151
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#define CLK_SCLK_UART1 152
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#define CLK_SCLK_UART2 153
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#define CLK_SCLK_UART3 154
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#define CLK_SCLK_UART4 155
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#define CLK_SCLK_AUDIO1 156
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#define CLK_SCLK_AUDIO2 157
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#define CLK_SCLK_SPDIF 158
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#define CLK_SCLK_SPI0 159
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#define CLK_SCLK_SPI1 160
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#define CLK_SCLK_SPI2 161
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#define CLK_SCLK_SLIMBUS 162
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#define CLK_SCLK_FIMD1 163 /* Exynos4210 only */
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#define CLK_SCLK_MIPI1 164 /* Exynos4210 only */
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#define CLK_SCLK_PCM1 165
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#define CLK_SCLK_PCM2 166
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#define CLK_SCLK_I2S1 167
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#define CLK_SCLK_I2S2 168
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#define CLK_SCLK_MIPIHSI 169 /* Exynos4412 only */
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#define CLK_SCLK_MFC 170
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#define CLK_SCLK_PCM0 171
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#define CLK_SCLK_G3D 172
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#define CLK_SCLK_PWM_ISP 173 /* Exynos4x12 only */
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#define CLK_SCLK_SPI0_ISP 174 /* Exynos4x12 only */
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#define CLK_SCLK_SPI1_ISP 175 /* Exynos4x12 only */
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#define CLK_SCLK_UART_ISP 176 /* Exynos4x12 only */
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#define CLK_SCLK_FIMG2D 177
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/* gate clocks */
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#define CLK_SSS 255
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#define CLK_FIMC0 256
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#define CLK_FIMC1 257
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#define CLK_FIMC2 258
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#define CLK_FIMC3 259
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#define CLK_CSIS0 260
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#define CLK_CSIS1 261
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#define CLK_JPEG 262
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#define CLK_SMMU_FIMC0 263
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#define CLK_SMMU_FIMC1 264
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#define CLK_SMMU_FIMC2 265
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#define CLK_SMMU_FIMC3 266
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#define CLK_SMMU_JPEG 267
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#define CLK_VP 268
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#define CLK_MIXER 269
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#define CLK_TVENC 270 /* Exynos4210 only */
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#define CLK_HDMI 271
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#define CLK_SMMU_TV 272
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#define CLK_MFC 273
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#define CLK_SMMU_MFCL 274
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#define CLK_SMMU_MFCR 275
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#define CLK_G3D 276
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#define CLK_G2D 277
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#define CLK_ROTATOR 278
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#define CLK_MDMA 279
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#define CLK_SMMU_G2D 280
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#define CLK_SMMU_ROTATOR 281
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#define CLK_SMMU_MDMA 282
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#define CLK_FIMD0 283
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#define CLK_MIE0 284
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#define CLK_MDNIE0 285 /* Exynos4412 only */
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#define CLK_DSIM0 286
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#define CLK_SMMU_FIMD0 287
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#define CLK_FIMD1 288 /* Exynos4210 only */
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#define CLK_MIE1 289 /* Exynos4210 only */
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#define CLK_DSIM1 290 /* Exynos4210 only */
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#define CLK_SMMU_FIMD1 291 /* Exynos4210 only */
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#define CLK_PDMA0 292
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#define CLK_PDMA1 293
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#define CLK_PCIE_PHY 294
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#define CLK_SATA_PHY 295 /* Exynos4210 only */
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#define CLK_TSI 296
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#define CLK_SDMMC0 297
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#define CLK_SDMMC1 298
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#define CLK_SDMMC2 299
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#define CLK_SDMMC3 300
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#define CLK_SDMMC4 301
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#define CLK_SATA 302 /* Exynos4210 only */
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#define CLK_SROMC 303
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#define CLK_USB_HOST 304
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#define CLK_USB_DEVICE 305
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#define CLK_PCIE 306
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#define CLK_ONENAND 307
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#define CLK_NFCON 308
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#define CLK_SMMU_PCIE 309
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#define CLK_GPS 310
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#define CLK_SMMU_GPS 311
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#define CLK_UART0 312
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#define CLK_UART1 313
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#define CLK_UART2 314
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#define CLK_UART3 315
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#define CLK_UART4 316
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#define CLK_I2C0 317
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#define CLK_I2C1 318
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#define CLK_I2C2 319
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#define CLK_I2C3 320
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#define CLK_I2C4 321
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#define CLK_I2C5 322
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#define CLK_I2C6 323
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#define CLK_I2C7 324
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#define CLK_I2C_HDMI 325
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#define CLK_TSADC 326
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#define CLK_SPI0 327
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#define CLK_SPI1 328
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#define CLK_SPI2 329
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#define CLK_I2S1 330
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#define CLK_I2S2 331
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#define CLK_PCM0 332
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#define CLK_I2S0 333
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#define CLK_PCM1 334
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#define CLK_PCM2 335
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#define CLK_PWM 336
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#define CLK_SLIMBUS 337
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#define CLK_SPDIF 338
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#define CLK_AC97 339
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#define CLK_MODEMIF 340
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#define CLK_CHIPID 341
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#define CLK_SYSREG 342
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#define CLK_HDMI_CEC 343
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#define CLK_MCT 344
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#define CLK_WDT 345
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#define CLK_RTC 346
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#define CLK_KEYIF 347
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#define CLK_AUDSS 348
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#define CLK_MIPI_HSI 349 /* Exynos4210 only */
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#define CLK_PIXELASYNCM0 351
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#define CLK_PIXELASYNCM1 352
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#define CLK_FIMC_LITE0 353 /* Exynos4x12 only */
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#define CLK_FIMC_LITE1 354 /* Exynos4x12 only */
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#define CLK_PPMUISPX 355 /* Exynos4x12 only */
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#define CLK_PPMUISPMX 356 /* Exynos4x12 only */
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#define CLK_FIMC_ISP 357 /* Exynos4x12 only */
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#define CLK_FIMC_DRC 358 /* Exynos4x12 only */
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#define CLK_FIMC_FD 359 /* Exynos4x12 only */
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#define CLK_MCUISP 360 /* Exynos4x12 only */
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#define CLK_GICISP 361 /* Exynos4x12 only */
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#define CLK_SMMU_ISP 362 /* Exynos4x12 only */
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#define CLK_SMMU_DRC 363 /* Exynos4x12 only */
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#define CLK_SMMU_FD 364 /* Exynos4x12 only */
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#define CLK_SMMU_LITE0 365 /* Exynos4x12 only */
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#define CLK_SMMU_LITE1 366 /* Exynos4x12 only */
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#define CLK_MCUCTL_ISP 367 /* Exynos4x12 only */
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#define CLK_MPWM_ISP 368 /* Exynos4x12 only */
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#define CLK_I2C0_ISP 369 /* Exynos4x12 only */
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#define CLK_I2C1_ISP 370 /* Exynos4x12 only */
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#define CLK_MTCADC_ISP 371 /* Exynos4x12 only */
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#define CLK_PWM_ISP 372 /* Exynos4x12 only */
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#define CLK_WDT_ISP 373 /* Exynos4x12 only */
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#define CLK_UART_ISP 374 /* Exynos4x12 only */
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#define CLK_ASYNCAXIM 375 /* Exynos4x12 only */
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#define CLK_SMMU_ISPCX 376 /* Exynos4x12 only */
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#define CLK_SPI0_ISP 377 /* Exynos4x12 only */
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#define CLK_SPI1_ISP 378 /* Exynos4x12 only */
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#define CLK_PWM_ISP_SCLK 379 /* Exynos4x12 only */
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#define CLK_SPI0_ISP_SCLK 380 /* Exynos4x12 only */
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#define CLK_SPI1_ISP_SCLK 381 /* Exynos4x12 only */
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#define CLK_UART_ISP_SCLK 382 /* Exynos4x12 only */
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#define CLK_TMU_APBIF 383
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/* mux clocks */
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#define CLK_MOUT_FIMC0 384
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#define CLK_MOUT_FIMC1 385
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#define CLK_MOUT_FIMC2 386
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#define CLK_MOUT_FIMC3 387
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#define CLK_MOUT_CAM0 388
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#define CLK_MOUT_CAM1 389
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#define CLK_MOUT_CSIS0 390
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#define CLK_MOUT_CSIS1 391
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#define CLK_MOUT_G3D0 392
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#define CLK_MOUT_G3D1 393
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#define CLK_MOUT_G3D 394
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#define CLK_ACLK400_MCUISP 395 /* Exynos4x12 only */
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#define CLK_MOUT_HDMI 396
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#define CLK_MOUT_MIXER 397
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/* gate clocks - ppmu */
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#define CLK_PPMULEFT 400
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#define CLK_PPMURIGHT 401
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#define CLK_PPMUCAMIF 402
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#define CLK_PPMUTV 403
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#define CLK_PPMUMFC_L 404
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#define CLK_PPMUMFC_R 405
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#define CLK_PPMUG3D 406
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#define CLK_PPMUIMAGE 407
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#define CLK_PPMULCD0 408
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#define CLK_PPMULCD1 409 /* Exynos4210 only */
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#define CLK_PPMUFILE 410
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#define CLK_PPMUGPS 411
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#define CLK_PPMUDMC0 412
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#define CLK_PPMUDMC1 413
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#define CLK_PPMUCPU 414
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#define CLK_PPMUACP 415
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/* div clocks */
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#define CLK_DIV_ISP0 450 /* Exynos4x12 only */
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#define CLK_DIV_ISP1 451 /* Exynos4x12 only */
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#define CLK_DIV_MCUISP0 452 /* Exynos4x12 only */
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#define CLK_DIV_MCUISP1 453 /* Exynos4x12 only */
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#define CLK_DIV_ACLK200 454 /* Exynos4x12 only */
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#define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */
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#define CLK_DIV_ACP 456
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#define CLK_DIV_DMC 457
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#define CLK_DIV_C2C 458 /* Exynos4x12 only */
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#define CLK_DIV_GDL 459
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#define CLK_DIV_GDR 460
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/* must be greater than maximal clock id */
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#define CLK_NR_CLKS 461
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/* Exynos4x12 ISP clocks */
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#define CLK_ISP_FIMC_ISP 1
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#define CLK_ISP_FIMC_DRC 2
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#define CLK_ISP_FIMC_FD 3
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#define CLK_ISP_FIMC_LITE0 4
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#define CLK_ISP_FIMC_LITE1 5
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#define CLK_ISP_MCUISP 6
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#define CLK_ISP_GICISP 7
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#define CLK_ISP_SMMU_ISP 8
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#define CLK_ISP_SMMU_DRC 9
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#define CLK_ISP_SMMU_FD 10
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#define CLK_ISP_SMMU_LITE0 11
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#define CLK_ISP_SMMU_LITE1 12
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#define CLK_ISP_PPMUISPMX 13
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#define CLK_ISP_PPMUISPX 14
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#define CLK_ISP_MCUCTL_ISP 15
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#define CLK_ISP_MPWM_ISP 16
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#define CLK_ISP_I2C0_ISP 17
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#define CLK_ISP_I2C1_ISP 18
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#define CLK_ISP_MTCADC_ISP 19
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#define CLK_ISP_PWM_ISP 20
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#define CLK_ISP_WDT_ISP 21
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#define CLK_ISP_UART_ISP 22
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#define CLK_ISP_ASYNCAXIM 23
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#define CLK_ISP_SMMU_ISPCX 24
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#define CLK_ISP_SPI0_ISP 25
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#define CLK_ISP_SPI1_ISP 26
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#define CLK_ISP_DIV_ISP0 27
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#define CLK_ISP_DIV_ISP1 28
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#define CLK_ISP_DIV_MCUISP0 29
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#define CLK_ISP_DIV_MCUISP1 30
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#define CLK_NR_ISP_CLKS 31
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#endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */
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