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abe60a3a7a
Remove the usage of skeleton.dtsi in the remaining dts files. It was
deprecated since commit 9c0da3cc61 ("ARM: dts: explicitly mark
skeleton.dtsi as deprecated"). This will make adding a unit-address to
memory nodes easier.
The main tricky part to removing skeleton.dtsi is we could end up with
no /memory node at all when a bootloader depends on one being present. I
hacked up dtc to check for this condition.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Antoine Tenart <antoine.tenart@bootlin.com>
Acked-by: Alexandre TORGUE <alexandre.torgue@st.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Acked-by: Vladimir Zapolskiy <vz@mleia.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Tested-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
1004 lines
27 KiB
Plaintext
1004 lines
27 KiB
Plaintext
/*
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* sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC
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*
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* Copyright (C) 2015 Atmel,
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* 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/dma/at91.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/clock/at91.h>
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#include <dt-bindings/iio/adc/at91-sama5d2_adc.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "Atmel SAMA5D2 family SoC";
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compatible = "atmel,sama5d2";
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interrupt-parent = <&aic>;
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aliases {
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serial0 = &uart1;
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serial1 = &uart3;
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tcb0 = &tcb0;
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tcb1 = &tcb1;
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i2s0 = &i2s0;
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i2s1 = &i2s1;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a5";
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reg = <0>;
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next-level-cache = <&L2>;
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};
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};
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pmu {
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compatible = "arm,cortex-a5-pmu";
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interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>;
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};
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etb {
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compatible = "arm,coresight-etb10", "arm,primecell";
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reg = <0x740000 0x1000>;
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clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
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clock-names = "apb_pclk";
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in-ports {
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port {
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etb_in: endpoint {
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remote-endpoint = <&etm_out>;
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};
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};
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};
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};
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etm {
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compatible = "arm,coresight-etm3x", "arm,primecell";
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reg = <0x73C000 0x1000>;
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clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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etm_out: endpoint {
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remote-endpoint = <&etb_in>;
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};
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};
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};
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};
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memory {
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device_type = "memory";
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reg = <0x20000000 0x20000000>;
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};
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clocks {
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slow_xtal: slow_xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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main_xtal: main_xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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};
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ns_sram: sram@200000 {
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compatible = "mmio-sram";
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reg = <0x00200000 0x20000>;
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};
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ahb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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nfc_sram: sram@100000 {
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compatible = "mmio-sram";
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no-memory-wc;
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reg = <0x00100000 0x2400>;
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};
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usb0: gadget@300000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "atmel,sama5d3-udc";
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reg = <0x00300000 0x100000
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0xfc02c000 0x400>;
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interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
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clock-names = "pclk", "hclk";
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status = "disabled";
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ep@0 {
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reg = <0>;
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atmel,fifo-size = <64>;
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atmel,nb-banks = <1>;
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};
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ep@1 {
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reg = <1>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <3>;
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atmel,can-dma;
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atmel,can-isoc;
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};
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ep@2 {
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reg = <2>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <3>;
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atmel,can-dma;
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atmel,can-isoc;
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};
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ep@3 {
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reg = <3>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-dma;
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atmel,can-isoc;
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};
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ep@4 {
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reg = <4>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-dma;
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atmel,can-isoc;
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};
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ep@5 {
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reg = <5>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-dma;
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atmel,can-isoc;
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};
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ep@6 {
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reg = <6>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-dma;
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atmel,can-isoc;
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};
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ep@7 {
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reg = <7>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-dma;
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atmel,can-isoc;
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};
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ep@8 {
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reg = <8>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-isoc;
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};
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ep@9 {
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reg = <9>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-isoc;
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};
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ep@10 {
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reg = <10>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-isoc;
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};
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ep@11 {
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reg = <11>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-isoc;
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};
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ep@12 {
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reg = <12>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-isoc;
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};
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ep@13 {
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reg = <13>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-isoc;
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};
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ep@14 {
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reg = <14>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-isoc;
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};
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ep@15 {
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reg = <15>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-isoc;
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};
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};
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usb1: ohci@400000 {
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compatible = "atmel,at91rm9200-ohci", "usb-ohci";
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reg = <0x00400000 0x100000>;
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interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_SYSTEM 6>;
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clock-names = "ohci_clk", "hclk", "uhpck";
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status = "disabled";
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};
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usb2: ehci@500000 {
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compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
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reg = <0x00500000 0x100000>;
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interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
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clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 41>;
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clock-names = "usb_clk", "ehci_clk";
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status = "disabled";
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};
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L2: cache-controller@a00000 {
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compatible = "arm,pl310-cache";
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reg = <0x00a00000 0x1000>;
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interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>;
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cache-unified;
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cache-level = <2>;
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};
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ebi: ebi@10000000 {
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compatible = "atmel,sama5d3-ebi";
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#address-cells = <2>;
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#size-cells = <1>;
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atmel,smc = <&hsmc>;
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reg = <0x10000000 0x10000000
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0x60000000 0x30000000>;
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ranges = <0x0 0x0 0x10000000 0x10000000
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0x1 0x0 0x60000000 0x10000000
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0x2 0x0 0x70000000 0x10000000
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0x3 0x0 0x80000000 0x10000000>;
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clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>;
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status = "disabled";
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nand_controller: nand-controller {
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compatible = "atmel,sama5d3-nand-controller";
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atmel,nfc-sram = <&nfc_sram>;
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atmel,nfc-io = <&nfc_io>;
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ecc-engine = <&pmecc>;
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#address-cells = <2>;
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#size-cells = <1>;
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ranges;
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status = "disabled";
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};
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};
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sdmmc0: sdio-host@a0000000 {
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compatible = "atmel,sama5d2-sdhci";
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reg = <0xa0000000 0x300>;
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interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 31>, <&pmc PMC_TYPE_GCK 31>, <&pmc PMC_TYPE_CORE PMC_MAIN>;
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clock-names = "hclock", "multclk", "baseclk";
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status = "disabled";
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};
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sdmmc1: sdio-host@b0000000 {
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compatible = "atmel,sama5d2-sdhci";
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reg = <0xb0000000 0x300>;
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interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_GCK 32>, <&pmc PMC_TYPE_CORE PMC_MAIN>;
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clock-names = "hclock", "multclk", "baseclk";
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status = "disabled";
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};
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nfc_io: nfc-io@c0000000 {
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compatible = "atmel,sama5d3-nfc-io", "syscon";
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reg = <0xc0000000 0x8000000>;
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};
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apb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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hlcdc: hlcdc@f0000000 {
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compatible = "atmel,sama5d2-hlcdc";
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reg = <0xf0000000 0x2000>;
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interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>;
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clock-names = "periph_clk","sys_clk", "slow_clk";
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status = "disabled";
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hlcdc-display-controller {
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compatible = "atmel,hlcdc-display-controller";
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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};
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};
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hlcdc_pwm: hlcdc-pwm {
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compatible = "atmel,hlcdc-pwm";
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#pwm-cells = <3>;
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};
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};
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isc: isc@f0008000 {
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compatible = "atmel,sama5d2-isc";
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reg = <0xf0008000 0x4000>;
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interrupts = <46 IRQ_TYPE_LEVEL_HIGH 5>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 18>, <&pmc PMC_TYPE_GCK 46>;
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clock-names = "hclock", "iscck", "gck";
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#clock-cells = <0>;
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clock-output-names = "isc-mck";
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status = "disabled";
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};
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ramc0: ramc@f000c000 {
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compatible = "atmel,sama5d3-ddramc";
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reg = <0xf000c000 0x200>;
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clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 13>;
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clock-names = "ddrck", "mpddr";
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};
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dma0: dma-controller@f0010000 {
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compatible = "atmel,sama5d4-dma";
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reg = <0xf0010000 0x1000>;
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interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
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#dma-cells = <1>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
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clock-names = "dma_clk";
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};
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/* Place dma1 here despite its address */
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dma1: dma-controller@f0004000 {
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compatible = "atmel,sama5d4-dma";
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reg = <0xf0004000 0x1000>;
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interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>;
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#dma-cells = <1>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
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clock-names = "dma_clk";
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};
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pmc: pmc@f0014000 {
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compatible = "atmel,sama5d2-pmc", "syscon";
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reg = <0xf0014000 0x160>;
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interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
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#clock-cells = <2>;
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clocks = <&clk32k>, <&main_xtal>;
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clock-names = "slow_clk", "main_xtal";
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};
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qspi0: spi@f0020000 {
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compatible = "atmel,sama5d2-qspi";
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reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>;
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reg-names = "qspi_base", "qspi_mmap";
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interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 52>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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qspi1: spi@f0024000 {
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compatible = "atmel,sama5d2-qspi";
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reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>;
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reg-names = "qspi_base", "qspi_mmap";
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interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 53>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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sha@f0028000 {
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compatible = "atmel,at91sam9g46-sha";
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reg = <0xf0028000 0x100>;
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interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
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dmas = <&dma0
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(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
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AT91_XDMAC_DT_PERID(30))>;
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dma-names = "tx";
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clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
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clock-names = "sha_clk";
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status = "okay";
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};
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aes@f002c000 {
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compatible = "atmel,at91sam9g46-aes";
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reg = <0xf002c000 0x100>;
|
|
interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(26))>,
|
|
<&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(27))>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
|
|
clock-names = "aes_clk";
|
|
status = "okay";
|
|
};
|
|
|
|
spi0: spi@f8000000 {
|
|
compatible = "atmel,at91rm9200-spi";
|
|
reg = <0xf8000000 0x100>;
|
|
interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(6))>,
|
|
<&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(7))>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
|
|
clock-names = "spi_clk";
|
|
atmel,fifo-size = <16>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ssc0: ssc@f8004000 {
|
|
compatible = "atmel,at91sam9g45-ssc";
|
|
reg = <0xf8004000 0x4000>;
|
|
interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(21))>,
|
|
<&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(22))>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
|
|
clock-names = "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
macb0: ethernet@f8008000 {
|
|
compatible = "atmel,sama5d2-gem";
|
|
reg = <0xf8008000 0x1000>;
|
|
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */
|
|
66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */
|
|
67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&pmc PMC_TYPE_PERIPHERAL 5>;
|
|
clock-names = "hclk", "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
tcb0: timer@f800c000 {
|
|
compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0xf800c000 0x100>;
|
|
interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&clk32k>;
|
|
clock-names = "t0_clk", "slow_clk";
|
|
};
|
|
|
|
tcb1: timer@f8010000 {
|
|
compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0xf8010000 0x100>;
|
|
interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&clk32k>;
|
|
clock-names = "t0_clk", "slow_clk";
|
|
};
|
|
|
|
hsmc: hsmc@f8014000 {
|
|
compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd";
|
|
reg = <0xf8014000 0x1000>;
|
|
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 17>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
pmecc: ecc-engine@f8014070 {
|
|
compatible = "atmel,sama5d2-pmecc";
|
|
reg = <0xf8014070 0x490>,
|
|
<0xf8014500 0x100>;
|
|
};
|
|
};
|
|
|
|
pdmic: pdmic@f8018000 {
|
|
compatible = "atmel,sama5d2-pdmic";
|
|
reg = <0xf8018000 0x124>;
|
|
interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
|
|
| AT91_XDMAC_DT_PERID(50))>;
|
|
dma-names = "rx";
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 48>, <&pmc PMC_TYPE_GCK 48>;
|
|
clock-names = "pclk", "gclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart0: serial@f801c000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xf801c000 0x100>;
|
|
interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(35))>,
|
|
<&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(36))>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 24>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@f8020000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xf8020000 0x100>;
|
|
interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(37))>,
|
|
<&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(38))>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 25>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@f8024000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xf8024000 0x100>;
|
|
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(39))>,
|
|
<&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(40))>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 26>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@f8028000 {
|
|
compatible = "atmel,sama5d2-i2c";
|
|
reg = <0xf8028000 0x100>;
|
|
interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(0))>,
|
|
<&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(1))>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
|
|
atmel,fifo-size = <16>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm0: pwm@f802c000 {
|
|
compatible = "atmel,sama5d2-pwm";
|
|
reg = <0xf802c000 0x4000>;
|
|
interrupts = <38 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
|
|
};
|
|
|
|
sfr: sfr@f8030000 {
|
|
compatible = "atmel,sama5d2-sfr", "syscon";
|
|
reg = <0xf8030000 0x98>;
|
|
};
|
|
|
|
flx0: flexcom@f8034000 {
|
|
compatible = "atmel,sama5d2-flexcom";
|
|
reg = <0xf8034000 0x200>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xf8034000 0x800>;
|
|
status = "disabled";
|
|
};
|
|
|
|
flx1: flexcom@f8038000 {
|
|
compatible = "atmel,sama5d2-flexcom";
|
|
reg = <0xf8038000 0x200>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xf8038000 0x800>;
|
|
status = "disabled";
|
|
};
|
|
|
|
securam: sram@f8044000 {
|
|
compatible = "atmel,sama5d2-securam", "mmio-sram";
|
|
reg = <0xf8044000 0x1420>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 51>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0xf8044000 0x1420>;
|
|
};
|
|
|
|
rstc@f8048000 {
|
|
compatible = "atmel,sama5d3-rstc";
|
|
reg = <0xf8048000 0x10>;
|
|
clocks = <&clk32k>;
|
|
};
|
|
|
|
shdwc@f8048010 {
|
|
compatible = "atmel,sama5d2-shdwc";
|
|
reg = <0xf8048010 0x10>;
|
|
clocks = <&clk32k>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
atmel,wakeup-rtc-timer;
|
|
};
|
|
|
|
pit: timer@f8048030 {
|
|
compatible = "atmel,at91sam9260-pit";
|
|
reg = <0xf8048030 0x10>;
|
|
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
|
|
clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>;
|
|
};
|
|
|
|
watchdog@f8048040 {
|
|
compatible = "atmel,sama5d4-wdt";
|
|
reg = <0xf8048040 0x10>;
|
|
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
clocks = <&clk32k>;
|
|
status = "disabled";
|
|
};
|
|
|
|
clk32k: sckc@f8048050 {
|
|
compatible = "atmel,sama5d4-sckc";
|
|
reg = <0xf8048050 0x4>;
|
|
|
|
clocks = <&slow_xtal>;
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
rtc@f80480b0 {
|
|
compatible = "atmel,at91rm9200-rtc";
|
|
reg = <0xf80480b0 0x30>;
|
|
interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
clocks = <&clk32k>;
|
|
};
|
|
|
|
i2s0: i2s@f8050000 {
|
|
compatible = "atmel,sama5d2-i2s";
|
|
reg = <0xf8050000 0x100>;
|
|
interrupts = <54 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(31))>,
|
|
<&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(32))>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_GCK 54>;
|
|
clock-names = "pclk", "gclk";
|
|
assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S0_MUX>;
|
|
assigned-clock-parents = <&pmc PMC_TYPE_GCK 54>;
|
|
status = "disabled";
|
|
};
|
|
|
|
can0: can@f8054000 {
|
|
compatible = "bosch,m_can";
|
|
reg = <0xf8054000 0x4000>, <0x210000 0x4000>;
|
|
reg-names = "m_can", "message_ram";
|
|
interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>,
|
|
<64 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
interrupt-names = "int0", "int1";
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 56>, <&pmc PMC_TYPE_GCK 56>;
|
|
clock-names = "hclk", "cclk";
|
|
assigned-clocks = <&pmc PMC_TYPE_GCK 56>;
|
|
assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
|
|
assigned-clock-rates = <40000000>;
|
|
bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi1: spi@fc000000 {
|
|
compatible = "atmel,at91rm9200-spi";
|
|
reg = <0xfc000000 0x100>;
|
|
interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(8))>,
|
|
<&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(9))>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 34>;
|
|
clock-names = "spi_clk";
|
|
atmel,fifo-size = <16>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@fc008000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xfc008000 0x100>;
|
|
interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
dmas = <&dma1
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(41))>,
|
|
<&dma1
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(42))>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 27>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@fc00c000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xfc00c000 0x100>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(43))>,
|
|
<&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(44))>;
|
|
dma-names = "tx", "rx";
|
|
interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
flx2: flexcom@fc010000 {
|
|
compatible = "atmel,sama5d2-flexcom";
|
|
reg = <0xfc010000 0x200>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xfc010000 0x800>;
|
|
status = "disabled";
|
|
};
|
|
|
|
flx3: flexcom@fc014000 {
|
|
compatible = "atmel,sama5d2-flexcom";
|
|
reg = <0xfc014000 0x200>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xfc014000 0x800>;
|
|
status = "disabled";
|
|
};
|
|
|
|
flx4: flexcom@fc018000 {
|
|
compatible = "atmel,sama5d2-flexcom";
|
|
reg = <0xfc018000 0x200>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xfc018000 0x800>;
|
|
status = "disabled";
|
|
};
|
|
|
|
trng@fc01c000 {
|
|
compatible = "atmel,at91sam9g45-trng";
|
|
reg = <0xfc01c000 0x100>;
|
|
interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
|
|
};
|
|
|
|
aic: interrupt-controller@fc020000 {
|
|
#interrupt-cells = <3>;
|
|
compatible = "atmel,sama5d2-aic";
|
|
interrupt-controller;
|
|
reg = <0xfc020000 0x200>;
|
|
atmel,external-irqs = <49>;
|
|
};
|
|
|
|
i2c1: i2c@fc028000 {
|
|
compatible = "atmel,sama5d2-i2c";
|
|
reg = <0xfc028000 0x100>;
|
|
interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(2))>,
|
|
<&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(3))>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
|
|
atmel,fifo-size = <16>;
|
|
status = "disabled";
|
|
};
|
|
|
|
adc: adc@fc030000 {
|
|
compatible = "atmel,sama5d2-adc";
|
|
reg = <0xfc030000 0x100>;
|
|
interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
|
|
clock-names = "adc_clk";
|
|
dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>;
|
|
dma-names = "rx";
|
|
atmel,min-sample-rate-hz = <200000>;
|
|
atmel,max-sample-rate-hz = <20000000>;
|
|
atmel,startup-time-ms = <4>;
|
|
atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>;
|
|
#io-channel-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
resistive_touch: resistive-touch {
|
|
compatible = "resistive-adc-touch";
|
|
io-channels = <&adc AT91_SAMA5D2_ADC_X_CHANNEL>,
|
|
<&adc AT91_SAMA5D2_ADC_Y_CHANNEL>,
|
|
<&adc AT91_SAMA5D2_ADC_P_CHANNEL>;
|
|
io-channel-names = "x", "y", "pressure";
|
|
touchscreen-min-pressure = <50000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pioA: pinctrl@fc038000 {
|
|
compatible = "atmel,sama5d2-pinctrl";
|
|
reg = <0xfc038000 0x600>;
|
|
interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>,
|
|
<68 IRQ_TYPE_LEVEL_HIGH 7>,
|
|
<69 IRQ_TYPE_LEVEL_HIGH 7>,
|
|
<70 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
|
|
};
|
|
|
|
secumod@fc040000 {
|
|
compatible = "atmel,sama5d2-secumod", "syscon";
|
|
reg = <0xfc040000 0x100>;
|
|
};
|
|
|
|
tdes@fc044000 {
|
|
compatible = "atmel,at91sam9g46-tdes";
|
|
reg = <0xfc044000 0x100>;
|
|
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(28))>,
|
|
<&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(29))>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
|
|
clock-names = "tdes_clk";
|
|
status = "okay";
|
|
};
|
|
|
|
classd: classd@fc048000 {
|
|
compatible = "atmel,sama5d2-classd";
|
|
reg = <0xfc048000 0x100>;
|
|
interrupts = <59 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(47))>;
|
|
dma-names = "tx";
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 59>, <&pmc PMC_TYPE_GCK 59>;
|
|
clock-names = "pclk", "gclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2s1: i2s@fc04c000 {
|
|
compatible = "atmel,sama5d2-i2s";
|
|
reg = <0xfc04c000 0x100>;
|
|
interrupts = <55 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(33))>,
|
|
<&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(34))>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_GCK 55>;
|
|
clock-names = "pclk", "gclk";
|
|
assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S1_MUX>;
|
|
assigned-parrents = <&pmc PMC_TYPE_GCK 55>;
|
|
status = "disabled";
|
|
};
|
|
|
|
can1: can@fc050000 {
|
|
compatible = "bosch,m_can";
|
|
reg = <0xfc050000 0x4000>, <0x210000 0x4000>;
|
|
reg-names = "m_can", "message_ram";
|
|
interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>,
|
|
<65 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
interrupt-names = "int0", "int1";
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>;
|
|
clock-names = "hclk", "cclk";
|
|
assigned-clocks = <&pmc PMC_TYPE_GCK 57>;
|
|
assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
|
|
assigned-clock-rates = <40000000>;
|
|
bosch,mram-cfg = <0x1100 0 0 64 0 0 32 32>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sfrbu: sfr@fc05c000 {
|
|
compatible = "atmel,sama5d2-sfrbu", "syscon";
|
|
reg = <0xfc05c000 0x20>;
|
|
};
|
|
|
|
chipid@fc069000 {
|
|
compatible = "atmel,sama5d2-chipid";
|
|
reg = <0xfc069000 0x8>;
|
|
};
|
|
};
|
|
};
|
|
};
|