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df561f6688
Replace the existing /* fall through */ comments and its variants with the new pseudo-keyword macro fallthrough[1]. Also, remove unnecessary fall-through markings when it is the case. [1] https://www.kernel.org/doc/html/v5.7/process/deprecated.html?highlight=fallthrough#implicit-switch-case-fall-through Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
798 lines
20 KiB
C
798 lines
20 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* linux/drivers/mmc/host/sdhci-s3c.c
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*
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* Copyright 2008 Openmoko Inc.
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* SDHCI (HSMMC) support for Samsung SoC
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*/
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#include <linux/spinlock.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/platform_device.h>
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#include <linux/platform_data/mmc-sdhci-s3c.h>
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_gpio.h>
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#include <linux/pm.h>
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#include <linux/pm_runtime.h>
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#include <linux/mmc/host.h>
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#include "sdhci.h"
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#define MAX_BUS_CLK (4)
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#define S3C_SDHCI_CONTROL2 (0x80)
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#define S3C_SDHCI_CONTROL3 (0x84)
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#define S3C64XX_SDHCI_CONTROL4 (0x8C)
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#define S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR BIT(31)
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#define S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK BIT(30)
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#define S3C_SDHCI_CTRL2_CDINVRXD3 BIT(29)
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#define S3C_SDHCI_CTRL2_SLCARDOUT BIT(28)
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#define S3C_SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24)
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#define S3C_SDHCI_CTRL2_FLTCLKSEL_SHIFT (24)
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#define S3C_SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24)
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#define S3C_SDHCI_CTRL2_LVLDAT_MASK (0xff << 16)
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#define S3C_SDHCI_CTRL2_LVLDAT_SHIFT (16)
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#define S3C_SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16)
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#define S3C_SDHCI_CTRL2_ENFBCLKTX BIT(15)
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#define S3C_SDHCI_CTRL2_ENFBCLKRX BIT(14)
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#define S3C_SDHCI_CTRL2_SDCDSEL BIT(13)
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#define S3C_SDHCI_CTRL2_SDSIGPC BIT(12)
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#define S3C_SDHCI_CTRL2_ENBUSYCHKTXSTART BIT(11)
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#define S3C_SDHCI_CTRL2_DFCNT_MASK (0x3 << 9)
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#define S3C_SDHCI_CTRL2_DFCNT_SHIFT (9)
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#define S3C_SDHCI_CTRL2_DFCNT_NONE (0x0 << 9)
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#define S3C_SDHCI_CTRL2_DFCNT_4SDCLK (0x1 << 9)
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#define S3C_SDHCI_CTRL2_DFCNT_16SDCLK (0x2 << 9)
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#define S3C_SDHCI_CTRL2_DFCNT_64SDCLK (0x3 << 9)
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#define S3C_SDHCI_CTRL2_ENCLKOUTHOLD BIT(8)
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#define S3C_SDHCI_CTRL2_RWAITMODE BIT(7)
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#define S3C_SDHCI_CTRL2_DISBUFRD BIT(6)
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#define S3C_SDHCI_CTRL2_SELBASECLK_MASK (0x3 << 4)
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#define S3C_SDHCI_CTRL2_SELBASECLK_SHIFT (4)
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#define S3C_SDHCI_CTRL2_PWRSYNC BIT(3)
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#define S3C_SDHCI_CTRL2_ENCLKOUTMSKCON BIT(1)
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#define S3C_SDHCI_CTRL2_HWINITFIN BIT(0)
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#define S3C_SDHCI_CTRL3_FCSEL3 BIT(31)
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#define S3C_SDHCI_CTRL3_FCSEL2 BIT(23)
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#define S3C_SDHCI_CTRL3_FCSEL1 BIT(15)
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#define S3C_SDHCI_CTRL3_FCSEL0 BIT(7)
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#define S3C_SDHCI_CTRL3_FIA3_MASK (0x7f << 24)
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#define S3C_SDHCI_CTRL3_FIA3_SHIFT (24)
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#define S3C_SDHCI_CTRL3_FIA3(_x) ((_x) << 24)
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#define S3C_SDHCI_CTRL3_FIA2_MASK (0x7f << 16)
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#define S3C_SDHCI_CTRL3_FIA2_SHIFT (16)
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#define S3C_SDHCI_CTRL3_FIA2(_x) ((_x) << 16)
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#define S3C_SDHCI_CTRL3_FIA1_MASK (0x7f << 8)
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#define S3C_SDHCI_CTRL3_FIA1_SHIFT (8)
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#define S3C_SDHCI_CTRL3_FIA1(_x) ((_x) << 8)
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#define S3C_SDHCI_CTRL3_FIA0_MASK (0x7f << 0)
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#define S3C_SDHCI_CTRL3_FIA0_SHIFT (0)
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#define S3C_SDHCI_CTRL3_FIA0(_x) ((_x) << 0)
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#define S3C64XX_SDHCI_CONTROL4_DRIVE_MASK (0x3 << 16)
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#define S3C64XX_SDHCI_CONTROL4_DRIVE_SHIFT (16)
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#define S3C64XX_SDHCI_CONTROL4_DRIVE_2mA (0x0 << 16)
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#define S3C64XX_SDHCI_CONTROL4_DRIVE_4mA (0x1 << 16)
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#define S3C64XX_SDHCI_CONTROL4_DRIVE_7mA (0x2 << 16)
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#define S3C64XX_SDHCI_CONTROL4_DRIVE_9mA (0x3 << 16)
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#define S3C64XX_SDHCI_CONTROL4_BUSY (1)
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/**
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* struct sdhci_s3c - S3C SDHCI instance
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* @host: The SDHCI host created
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* @pdev: The platform device we where created from.
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* @ioarea: The resource created when we claimed the IO area.
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* @pdata: The platform data for this controller.
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* @cur_clk: The index of the current bus clock.
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* @ext_cd_irq: External card detect interrupt.
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* @clk_io: The clock for the internal bus interface.
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* @clk_rates: Clock frequencies.
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* @clk_bus: The clocks that are available for the SD/MMC bus clock.
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* @no_divider: No or non-standard internal clock divider.
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*/
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struct sdhci_s3c {
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struct sdhci_host *host;
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struct platform_device *pdev;
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struct resource *ioarea;
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struct s3c_sdhci_platdata *pdata;
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int cur_clk;
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int ext_cd_irq;
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struct clk *clk_io;
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struct clk *clk_bus[MAX_BUS_CLK];
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unsigned long clk_rates[MAX_BUS_CLK];
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bool no_divider;
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};
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/**
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* struct sdhci_s3c_driver_data - S3C SDHCI platform specific driver data
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* @sdhci_quirks: sdhci host specific quirks.
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* @no_divider: no or non-standard internal clock divider.
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*
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* Specifies platform specific configuration of sdhci controller.
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* Note: A structure for driver specific platform data is used for future
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* expansion of its usage.
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*/
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struct sdhci_s3c_drv_data {
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unsigned int sdhci_quirks;
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bool no_divider;
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};
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static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host)
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{
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return sdhci_priv(host);
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}
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/**
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* sdhci_s3c_get_max_clk - callback to get maximum clock frequency.
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* @host: The SDHCI host instance.
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*
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* Callback to return the maximum clock rate acheivable by the controller.
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*/
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static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host)
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{
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struct sdhci_s3c *ourhost = to_s3c(host);
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unsigned long rate, max = 0;
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int src;
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for (src = 0; src < MAX_BUS_CLK; src++) {
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rate = ourhost->clk_rates[src];
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if (rate > max)
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max = rate;
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}
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return max;
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}
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/**
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* sdhci_s3c_consider_clock - consider one the bus clocks for current setting
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* @ourhost: Our SDHCI instance.
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* @src: The source clock index.
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* @wanted: The clock frequency wanted.
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*/
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static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost,
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unsigned int src,
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unsigned int wanted)
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{
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unsigned long rate;
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struct clk *clksrc = ourhost->clk_bus[src];
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int shift;
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if (IS_ERR(clksrc))
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return UINT_MAX;
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/*
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* If controller uses a non-standard clock division, find the best clock
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* speed possible with selected clock source and skip the division.
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*/
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if (ourhost->no_divider) {
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rate = clk_round_rate(clksrc, wanted);
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return wanted - rate;
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}
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rate = ourhost->clk_rates[src];
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for (shift = 0; shift <= 8; ++shift) {
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if ((rate >> shift) <= wanted)
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break;
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}
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if (shift > 8) {
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dev_dbg(&ourhost->pdev->dev,
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"clk %d: rate %ld, min rate %lu > wanted %u\n",
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src, rate, rate / 256, wanted);
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return UINT_MAX;
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}
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dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n",
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src, rate, wanted, rate >> shift);
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return wanted - (rate >> shift);
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}
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/**
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* sdhci_s3c_set_clock - callback on clock change
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* @host: The SDHCI host being changed
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* @clock: The clock rate being requested.
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*
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* When the card's clock is going to be changed, look at the new frequency
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* and find the best clock source to go with it.
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*/
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static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock)
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{
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struct sdhci_s3c *ourhost = to_s3c(host);
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unsigned int best = UINT_MAX;
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unsigned int delta;
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int best_src = 0;
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int src;
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u32 ctrl;
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host->mmc->actual_clock = 0;
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/* don't bother if the clock is going off. */
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if (clock == 0) {
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sdhci_set_clock(host, clock);
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return;
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}
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for (src = 0; src < MAX_BUS_CLK; src++) {
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delta = sdhci_s3c_consider_clock(ourhost, src, clock);
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if (delta < best) {
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best = delta;
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best_src = src;
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}
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}
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dev_dbg(&ourhost->pdev->dev,
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"selected source %d, clock %d, delta %d\n",
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best_src, clock, best);
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/* select the new clock source */
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if (ourhost->cur_clk != best_src) {
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struct clk *clk = ourhost->clk_bus[best_src];
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clk_prepare_enable(clk);
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if (ourhost->cur_clk >= 0)
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clk_disable_unprepare(
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ourhost->clk_bus[ourhost->cur_clk]);
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ourhost->cur_clk = best_src;
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host->max_clk = ourhost->clk_rates[best_src];
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}
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/* turn clock off to card before changing clock source */
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writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
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ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
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ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
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ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
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writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
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/* reprogram default hardware configuration */
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writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA,
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host->ioaddr + S3C64XX_SDHCI_CONTROL4);
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ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
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ctrl |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
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S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
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S3C_SDHCI_CTRL2_ENFBCLKRX |
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S3C_SDHCI_CTRL2_DFCNT_NONE |
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S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
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writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
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/* reconfigure the controller for new clock rate */
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ctrl = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
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if (clock < 25 * 1000000)
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ctrl |= (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2);
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writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3);
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sdhci_set_clock(host, clock);
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}
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/**
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* sdhci_s3c_get_min_clock - callback to get minimal supported clock value
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* @host: The SDHCI host being queried
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*
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* To init mmc host properly a minimal clock value is needed. For high system
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* bus clock's values the standard formula gives values out of allowed range.
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* The clock still can be set to lower values, if clock source other then
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* system bus is selected.
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*/
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static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host)
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{
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struct sdhci_s3c *ourhost = to_s3c(host);
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unsigned long rate, min = ULONG_MAX;
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int src;
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for (src = 0; src < MAX_BUS_CLK; src++) {
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rate = ourhost->clk_rates[src] / 256;
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if (!rate)
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continue;
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if (rate < min)
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min = rate;
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}
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return min;
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}
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/* sdhci_cmu_get_max_clk - callback to get maximum clock frequency.*/
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static unsigned int sdhci_cmu_get_max_clock(struct sdhci_host *host)
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{
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struct sdhci_s3c *ourhost = to_s3c(host);
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unsigned long rate, max = 0;
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int src;
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for (src = 0; src < MAX_BUS_CLK; src++) {
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struct clk *clk;
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clk = ourhost->clk_bus[src];
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if (IS_ERR(clk))
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continue;
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rate = clk_round_rate(clk, ULONG_MAX);
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if (rate > max)
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max = rate;
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}
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return max;
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}
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/* sdhci_cmu_get_min_clock - callback to get minimal supported clock value. */
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static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host *host)
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{
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struct sdhci_s3c *ourhost = to_s3c(host);
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unsigned long rate, min = ULONG_MAX;
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int src;
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for (src = 0; src < MAX_BUS_CLK; src++) {
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struct clk *clk;
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clk = ourhost->clk_bus[src];
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if (IS_ERR(clk))
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continue;
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rate = clk_round_rate(clk, 0);
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if (rate < min)
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min = rate;
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}
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return min;
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}
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/* sdhci_cmu_set_clock - callback on clock change.*/
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static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock)
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{
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struct sdhci_s3c *ourhost = to_s3c(host);
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struct device *dev = &ourhost->pdev->dev;
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unsigned long timeout;
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u16 clk = 0;
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int ret;
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host->mmc->actual_clock = 0;
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/* If the clock is going off, set to 0 at clock control register */
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if (clock == 0) {
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sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
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return;
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}
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sdhci_s3c_set_clock(host, clock);
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/* Reset SD Clock Enable */
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clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
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clk &= ~SDHCI_CLOCK_CARD_EN;
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sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
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ret = clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock);
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if (ret != 0) {
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dev_err(dev, "%s: failed to set clock rate %uHz\n",
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mmc_hostname(host->mmc), clock);
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return;
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}
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clk = SDHCI_CLOCK_INT_EN;
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sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
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/* Wait max 20 ms */
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timeout = 20;
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while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
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& SDHCI_CLOCK_INT_STABLE)) {
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if (timeout == 0) {
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dev_err(dev, "%s: Internal clock never stabilised.\n",
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mmc_hostname(host->mmc));
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return;
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}
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timeout--;
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mdelay(1);
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}
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clk |= SDHCI_CLOCK_CARD_EN;
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sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
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}
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static struct sdhci_ops sdhci_s3c_ops = {
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.get_max_clock = sdhci_s3c_get_max_clk,
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.set_clock = sdhci_s3c_set_clock,
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.get_min_clock = sdhci_s3c_get_min_clock,
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.set_bus_width = sdhci_set_bus_width,
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.reset = sdhci_reset,
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.set_uhs_signaling = sdhci_set_uhs_signaling,
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};
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#ifdef CONFIG_OF
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static int sdhci_s3c_parse_dt(struct device *dev,
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struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
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{
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struct device_node *node = dev->of_node;
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u32 max_width;
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/* if the bus-width property is not specified, assume width as 1 */
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if (of_property_read_u32(node, "bus-width", &max_width))
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max_width = 1;
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pdata->max_width = max_width;
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/* get the card detection method */
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if (of_get_property(node, "broken-cd", NULL)) {
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pdata->cd_type = S3C_SDHCI_CD_NONE;
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return 0;
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}
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if (of_get_property(node, "non-removable", NULL)) {
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pdata->cd_type = S3C_SDHCI_CD_PERMANENT;
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return 0;
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}
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if (of_get_named_gpio(node, "cd-gpios", 0))
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return 0;
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/* assuming internal card detect that will be configured by pinctrl */
|
|
pdata->cd_type = S3C_SDHCI_CD_INTERNAL;
|
|
return 0;
|
|
}
|
|
#else
|
|
static int sdhci_s3c_parse_dt(struct device *dev,
|
|
struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
|
|
{
|
|
return -EINVAL;
|
|
}
|
|
#endif
|
|
|
|
static const struct of_device_id sdhci_s3c_dt_match[];
|
|
|
|
static inline struct sdhci_s3c_drv_data *sdhci_s3c_get_driver_data(
|
|
struct platform_device *pdev)
|
|
{
|
|
#ifdef CONFIG_OF
|
|
if (pdev->dev.of_node) {
|
|
const struct of_device_id *match;
|
|
match = of_match_node(sdhci_s3c_dt_match, pdev->dev.of_node);
|
|
return (struct sdhci_s3c_drv_data *)match->data;
|
|
}
|
|
#endif
|
|
return (struct sdhci_s3c_drv_data *)
|
|
platform_get_device_id(pdev)->driver_data;
|
|
}
|
|
|
|
static int sdhci_s3c_probe(struct platform_device *pdev)
|
|
{
|
|
struct s3c_sdhci_platdata *pdata;
|
|
struct sdhci_s3c_drv_data *drv_data;
|
|
struct device *dev = &pdev->dev;
|
|
struct sdhci_host *host;
|
|
struct sdhci_s3c *sc;
|
|
int ret, irq, ptr, clks;
|
|
|
|
if (!pdev->dev.platform_data && !pdev->dev.of_node) {
|
|
dev_err(dev, "no device data specified\n");
|
|
return -ENOENT;
|
|
}
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0)
|
|
return irq;
|
|
|
|
host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c));
|
|
if (IS_ERR(host)) {
|
|
dev_err(dev, "sdhci_alloc_host() failed\n");
|
|
return PTR_ERR(host);
|
|
}
|
|
sc = sdhci_priv(host);
|
|
|
|
pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
|
|
if (!pdata) {
|
|
ret = -ENOMEM;
|
|
goto err_pdata_io_clk;
|
|
}
|
|
|
|
if (pdev->dev.of_node) {
|
|
ret = sdhci_s3c_parse_dt(&pdev->dev, host, pdata);
|
|
if (ret)
|
|
goto err_pdata_io_clk;
|
|
} else {
|
|
memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata));
|
|
}
|
|
|
|
drv_data = sdhci_s3c_get_driver_data(pdev);
|
|
|
|
sc->host = host;
|
|
sc->pdev = pdev;
|
|
sc->pdata = pdata;
|
|
sc->cur_clk = -1;
|
|
|
|
platform_set_drvdata(pdev, host);
|
|
|
|
sc->clk_io = devm_clk_get(dev, "hsmmc");
|
|
if (IS_ERR(sc->clk_io)) {
|
|
dev_err(dev, "failed to get io clock\n");
|
|
ret = PTR_ERR(sc->clk_io);
|
|
goto err_pdata_io_clk;
|
|
}
|
|
|
|
/* enable the local io clock and keep it running for the moment. */
|
|
clk_prepare_enable(sc->clk_io);
|
|
|
|
for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
|
|
char name[14];
|
|
|
|
snprintf(name, 14, "mmc_busclk.%d", ptr);
|
|
sc->clk_bus[ptr] = devm_clk_get(dev, name);
|
|
if (IS_ERR(sc->clk_bus[ptr]))
|
|
continue;
|
|
|
|
clks++;
|
|
sc->clk_rates[ptr] = clk_get_rate(sc->clk_bus[ptr]);
|
|
|
|
dev_info(dev, "clock source %d: %s (%ld Hz)\n",
|
|
ptr, name, sc->clk_rates[ptr]);
|
|
}
|
|
|
|
if (clks == 0) {
|
|
dev_err(dev, "failed to find any bus clocks\n");
|
|
ret = -ENOENT;
|
|
goto err_no_busclks;
|
|
}
|
|
|
|
host->ioaddr = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(host->ioaddr)) {
|
|
ret = PTR_ERR(host->ioaddr);
|
|
goto err_req_regs;
|
|
}
|
|
|
|
/* Ensure we have minimal gpio selected CMD/CLK/Detect */
|
|
if (pdata->cfg_gpio)
|
|
pdata->cfg_gpio(pdev, pdata->max_width);
|
|
|
|
host->hw_name = "samsung-hsmmc";
|
|
host->ops = &sdhci_s3c_ops;
|
|
host->quirks = 0;
|
|
host->quirks2 = 0;
|
|
host->irq = irq;
|
|
|
|
/* Setup quirks for the controller */
|
|
host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
|
|
host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
|
|
if (drv_data) {
|
|
host->quirks |= drv_data->sdhci_quirks;
|
|
sc->no_divider = drv_data->no_divider;
|
|
}
|
|
|
|
#ifndef CONFIG_MMC_SDHCI_S3C_DMA
|
|
|
|
/* we currently see overruns on errors, so disable the SDMA
|
|
* support as well. */
|
|
host->quirks |= SDHCI_QUIRK_BROKEN_DMA;
|
|
|
|
#endif /* CONFIG_MMC_SDHCI_S3C_DMA */
|
|
|
|
/* It seems we do not get an DATA transfer complete on non-busy
|
|
* transfers, not sure if this is a problem with this specific
|
|
* SDHCI block, or a missing configuration that needs to be set. */
|
|
host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ;
|
|
|
|
/* This host supports the Auto CMD12 */
|
|
host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
|
|
|
|
/* Samsung SoCs need BROKEN_ADMA_ZEROLEN_DESC */
|
|
host->quirks |= SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC;
|
|
|
|
if (pdata->cd_type == S3C_SDHCI_CD_NONE ||
|
|
pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
|
|
host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
|
|
|
|
if (pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
|
|
host->mmc->caps = MMC_CAP_NONREMOVABLE;
|
|
|
|
switch (pdata->max_width) {
|
|
case 8:
|
|
host->mmc->caps |= MMC_CAP_8_BIT_DATA;
|
|
fallthrough;
|
|
case 4:
|
|
host->mmc->caps |= MMC_CAP_4_BIT_DATA;
|
|
break;
|
|
}
|
|
|
|
if (pdata->pm_caps)
|
|
host->mmc->pm_caps |= pdata->pm_caps;
|
|
|
|
host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
|
|
SDHCI_QUIRK_32BIT_DMA_SIZE);
|
|
|
|
/* HSMMC on Samsung SoCs uses SDCLK as timeout clock */
|
|
host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
|
|
|
|
/*
|
|
* If controller does not have internal clock divider,
|
|
* we can use overriding functions instead of default.
|
|
*/
|
|
if (sc->no_divider) {
|
|
sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock;
|
|
sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock;
|
|
sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock;
|
|
}
|
|
|
|
/* It supports additional host capabilities if needed */
|
|
if (pdata->host_caps)
|
|
host->mmc->caps |= pdata->host_caps;
|
|
|
|
if (pdata->host_caps2)
|
|
host->mmc->caps2 |= pdata->host_caps2;
|
|
|
|
pm_runtime_enable(&pdev->dev);
|
|
pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
|
|
pm_runtime_use_autosuspend(&pdev->dev);
|
|
pm_suspend_ignore_children(&pdev->dev, 1);
|
|
|
|
ret = mmc_of_parse(host->mmc);
|
|
if (ret)
|
|
goto err_req_regs;
|
|
|
|
ret = sdhci_add_host(host);
|
|
if (ret)
|
|
goto err_req_regs;
|
|
|
|
#ifdef CONFIG_PM
|
|
if (pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
|
|
clk_disable_unprepare(sc->clk_io);
|
|
#endif
|
|
return 0;
|
|
|
|
err_req_regs:
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
err_no_busclks:
|
|
clk_disable_unprepare(sc->clk_io);
|
|
|
|
err_pdata_io_clk:
|
|
sdhci_free_host(host);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int sdhci_s3c_remove(struct platform_device *pdev)
|
|
{
|
|
struct sdhci_host *host = platform_get_drvdata(pdev);
|
|
struct sdhci_s3c *sc = sdhci_priv(host);
|
|
|
|
if (sc->ext_cd_irq)
|
|
free_irq(sc->ext_cd_irq, sc);
|
|
|
|
#ifdef CONFIG_PM
|
|
if (sc->pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
|
|
clk_prepare_enable(sc->clk_io);
|
|
#endif
|
|
sdhci_remove_host(host, 1);
|
|
|
|
pm_runtime_dont_use_autosuspend(&pdev->dev);
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
clk_disable_unprepare(sc->clk_io);
|
|
|
|
sdhci_free_host(host);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int sdhci_s3c_suspend(struct device *dev)
|
|
{
|
|
struct sdhci_host *host = dev_get_drvdata(dev);
|
|
|
|
if (host->tuning_mode != SDHCI_TUNING_MODE_3)
|
|
mmc_retune_needed(host->mmc);
|
|
|
|
return sdhci_suspend_host(host);
|
|
}
|
|
|
|
static int sdhci_s3c_resume(struct device *dev)
|
|
{
|
|
struct sdhci_host *host = dev_get_drvdata(dev);
|
|
|
|
return sdhci_resume_host(host);
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_PM
|
|
static int sdhci_s3c_runtime_suspend(struct device *dev)
|
|
{
|
|
struct sdhci_host *host = dev_get_drvdata(dev);
|
|
struct sdhci_s3c *ourhost = to_s3c(host);
|
|
struct clk *busclk = ourhost->clk_io;
|
|
int ret;
|
|
|
|
ret = sdhci_runtime_suspend_host(host);
|
|
|
|
if (host->tuning_mode != SDHCI_TUNING_MODE_3)
|
|
mmc_retune_needed(host->mmc);
|
|
|
|
if (ourhost->cur_clk >= 0)
|
|
clk_disable_unprepare(ourhost->clk_bus[ourhost->cur_clk]);
|
|
clk_disable_unprepare(busclk);
|
|
return ret;
|
|
}
|
|
|
|
static int sdhci_s3c_runtime_resume(struct device *dev)
|
|
{
|
|
struct sdhci_host *host = dev_get_drvdata(dev);
|
|
struct sdhci_s3c *ourhost = to_s3c(host);
|
|
struct clk *busclk = ourhost->clk_io;
|
|
int ret;
|
|
|
|
clk_prepare_enable(busclk);
|
|
if (ourhost->cur_clk >= 0)
|
|
clk_prepare_enable(ourhost->clk_bus[ourhost->cur_clk]);
|
|
ret = sdhci_runtime_resume_host(host, 0);
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
static const struct dev_pm_ops sdhci_s3c_pmops = {
|
|
SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume)
|
|
SET_RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend, sdhci_s3c_runtime_resume,
|
|
NULL)
|
|
};
|
|
|
|
static const struct platform_device_id sdhci_s3c_driver_ids[] = {
|
|
{
|
|
.name = "s3c-sdhci",
|
|
.driver_data = (kernel_ulong_t)NULL,
|
|
},
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(platform, sdhci_s3c_driver_ids);
|
|
|
|
#ifdef CONFIG_OF
|
|
static struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = {
|
|
.no_divider = true,
|
|
};
|
|
|
|
static const struct of_device_id sdhci_s3c_dt_match[] = {
|
|
{ .compatible = "samsung,s3c6410-sdhci", },
|
|
{ .compatible = "samsung,exynos4210-sdhci",
|
|
.data = &exynos4_sdhci_drv_data },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, sdhci_s3c_dt_match);
|
|
#endif
|
|
|
|
static struct platform_driver sdhci_s3c_driver = {
|
|
.probe = sdhci_s3c_probe,
|
|
.remove = sdhci_s3c_remove,
|
|
.id_table = sdhci_s3c_driver_ids,
|
|
.driver = {
|
|
.name = "s3c-sdhci",
|
|
.of_match_table = of_match_ptr(sdhci_s3c_dt_match),
|
|
.pm = &sdhci_s3c_pmops,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(sdhci_s3c_driver);
|
|
|
|
MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue");
|
|
MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_ALIAS("platform:s3c-sdhci");
|