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990a40079a
SoCs that contain MDP5 have a top level wrapper called MDSS that manages clocks, power and irq for the sub-blocks within it. Currently, the MDSS portions are stuffed into the MDP5 driver. This makes it hard to represent the DT bindings in the correct way. We create a top level MDSS helper that handles these parts. This is essentially moving out some of the mdp5_kms irq code and MDSS register space and keeping it as a separate entity. We haven't given any clocks to the top level MDSS yet, but a AHB clock would be added in the future to access registers. One thing to note is that the resources allocated by this helper are tied to the top level platform_device (the one that allocates the drm_device struct too). This device would be the parent to MDSS sub-blocks like MDP5, DSI, eDP etc. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
82 lines
2.0 KiB
Makefile
82 lines
2.0 KiB
Makefile
ccflags-y := -Iinclude/drm -Idrivers/gpu/drm/msm
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ccflags-$(CONFIG_DRM_MSM_DSI) += -Idrivers/gpu/drm/msm/dsi
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msm-y := \
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adreno/adreno_device.o \
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adreno/adreno_gpu.o \
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adreno/a3xx_gpu.o \
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adreno/a4xx_gpu.o \
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hdmi/hdmi.o \
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hdmi/hdmi_audio.o \
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hdmi/hdmi_bridge.o \
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hdmi/hdmi_connector.o \
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hdmi/hdmi_i2c.o \
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hdmi/hdmi_phy.o \
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hdmi/hdmi_phy_8960.o \
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hdmi/hdmi_phy_8x60.o \
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hdmi/hdmi_phy_8x74.o \
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edp/edp.o \
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edp/edp_aux.o \
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edp/edp_bridge.o \
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edp/edp_connector.o \
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edp/edp_ctrl.o \
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edp/edp_phy.o \
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mdp/mdp_format.o \
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mdp/mdp_kms.o \
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mdp/mdp4/mdp4_crtc.o \
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mdp/mdp4/mdp4_dtv_encoder.o \
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mdp/mdp4/mdp4_lcdc_encoder.o \
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mdp/mdp4/mdp4_lvds_connector.o \
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mdp/mdp4/mdp4_irq.o \
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mdp/mdp4/mdp4_kms.o \
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mdp/mdp4/mdp4_plane.o \
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mdp/mdp5/mdp5_cfg.o \
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mdp/mdp5/mdp5_ctl.o \
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mdp/mdp5/mdp5_crtc.o \
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mdp/mdp5/mdp5_encoder.o \
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mdp/mdp5/mdp5_irq.o \
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mdp/mdp5/mdp5_mdss.o \
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mdp/mdp5/mdp5_kms.o \
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mdp/mdp5/mdp5_plane.o \
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mdp/mdp5/mdp5_smp.o \
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msm_atomic.o \
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msm_debugfs.o \
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msm_drv.o \
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msm_fb.o \
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msm_fence.o \
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msm_gem.o \
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msm_gem_prime.o \
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msm_gem_submit.o \
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msm_gpu.o \
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msm_iommu.o \
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msm_perf.o \
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msm_rd.o \
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msm_ringbuffer.o
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msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o
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msm-$(CONFIG_COMMON_CLK) += mdp/mdp4/mdp4_lvds_pll.o
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msm-$(CONFIG_COMMON_CLK) += hdmi/hdmi_pll_8960.o
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msm-$(CONFIG_COMMON_CLK) += hdmi/hdmi_phy_8996.o
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msm-$(CONFIG_DRM_MSM_HDMI_HDCP) += hdmi/hdmi_hdcp.o
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msm-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \
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mdp/mdp4/mdp4_dsi_encoder.o \
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dsi/dsi_cfg.o \
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dsi/dsi_host.o \
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dsi/dsi_manager.o \
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dsi/phy/dsi_phy.o \
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mdp/mdp5/mdp5_cmd_encoder.o
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msm-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/phy/dsi_phy_28nm.o
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msm-$(CONFIG_DRM_MSM_DSI_20NM_PHY) += dsi/phy/dsi_phy_20nm.o
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msm-$(CONFIG_DRM_MSM_DSI_28NM_8960_PHY) += dsi/phy/dsi_phy_28nm_8960.o
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ifeq ($(CONFIG_DRM_MSM_DSI_PLL),y)
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msm-y += dsi/pll/dsi_pll.o
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msm-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/pll/dsi_pll_28nm.o
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msm-$(CONFIG_DRM_MSM_DSI_28NM_8960_PHY) += dsi/pll/dsi_pll_28nm_8960.o
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endif
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obj-$(CONFIG_DRM_MSM) += msm.o
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