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05e2190eae
Ensure that the definitions of functions match the prototypes used by other modules by including the header with the prototypes in the files with the definitions. Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
619 lines
16 KiB
C
619 lines
16 KiB
C
/* linux/drivers/video/exynos/exynos_mipi_dsi_lowlevel.c
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*
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* Samsung SoC MIPI-DSI lowlevel driver.
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*
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* Copyright (c) 2012 Samsung Electronics Co., Ltd
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*
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* InKi Dae, <inki.dae@samsung.com>
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* Donghwa Lee, <dh09.lee@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/mutex.h>
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#include <linux/wait.h>
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#include <linux/delay.h>
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#include <linux/fs.h>
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#include <linux/mm.h>
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#include <linux/ctype.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <video/exynos_mipi_dsim.h>
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#include "exynos_mipi_dsi_regs.h"
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#include "exynos_mipi_dsi_lowlevel.h"
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void exynos_mipi_dsi_func_reset(struct mipi_dsim_device *dsim)
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{
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unsigned int reg;
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reg = readl(dsim->reg_base + EXYNOS_DSIM_SWRST);
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reg |= DSIM_FUNCRST;
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writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST);
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}
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void exynos_mipi_dsi_sw_reset(struct mipi_dsim_device *dsim)
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{
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unsigned int reg;
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reg = readl(dsim->reg_base + EXYNOS_DSIM_SWRST);
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reg |= DSIM_SWRST;
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writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST);
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}
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void exynos_mipi_dsi_sw_reset_release(struct mipi_dsim_device *dsim)
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{
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unsigned int reg;
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reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC);
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reg |= INTSRC_SW_RST_RELEASE;
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writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC);
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}
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int exynos_mipi_dsi_get_sw_reset_release(struct mipi_dsim_device *dsim)
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{
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return (readl(dsim->reg_base + EXYNOS_DSIM_INTSRC)) &
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INTSRC_SW_RST_RELEASE;
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}
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unsigned int exynos_mipi_dsi_read_interrupt_mask(struct mipi_dsim_device *dsim)
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{
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unsigned int reg;
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reg = readl(dsim->reg_base + EXYNOS_DSIM_INTMSK);
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return reg;
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}
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void exynos_mipi_dsi_set_interrupt_mask(struct mipi_dsim_device *dsim,
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unsigned int mode, unsigned int mask)
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{
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unsigned int reg = 0;
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if (mask)
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reg |= mode;
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else
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reg &= ~mode;
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writel(reg, dsim->reg_base + EXYNOS_DSIM_INTMSK);
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}
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void exynos_mipi_dsi_init_fifo_pointer(struct mipi_dsim_device *dsim,
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unsigned int cfg)
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{
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unsigned int reg;
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reg = readl(dsim->reg_base + EXYNOS_DSIM_FIFOCTRL);
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writel(reg & ~(cfg), dsim->reg_base + EXYNOS_DSIM_FIFOCTRL);
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mdelay(10);
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reg |= cfg;
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writel(reg, dsim->reg_base + EXYNOS_DSIM_FIFOCTRL);
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}
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/*
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* this function set PLL P, M and S value in D-PHY
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*/
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void exynos_mipi_dsi_set_phy_tunning(struct mipi_dsim_device *dsim,
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unsigned int value)
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{
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writel(DSIM_AFC_CTL(value), dsim->reg_base + EXYNOS_DSIM_PHYACCHR);
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}
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void exynos_mipi_dsi_set_main_stand_by(struct mipi_dsim_device *dsim,
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unsigned int enable)
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{
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unsigned int reg;
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reg = readl(dsim->reg_base + EXYNOS_DSIM_MDRESOL);
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reg &= ~DSIM_MAIN_STAND_BY;
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if (enable)
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reg |= DSIM_MAIN_STAND_BY;
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writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL);
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}
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void exynos_mipi_dsi_set_main_disp_resol(struct mipi_dsim_device *dsim,
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unsigned int width_resol, unsigned int height_resol)
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{
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unsigned int reg;
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/* standby should be set after configuration so set to not ready*/
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reg = (readl(dsim->reg_base + EXYNOS_DSIM_MDRESOL)) &
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~(DSIM_MAIN_STAND_BY);
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writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL);
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reg &= ~((0x7ff << 16) | (0x7ff << 0));
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reg |= DSIM_MAIN_VRESOL(height_resol) | DSIM_MAIN_HRESOL(width_resol);
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reg |= DSIM_MAIN_STAND_BY;
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writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL);
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}
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void exynos_mipi_dsi_set_main_disp_vporch(struct mipi_dsim_device *dsim,
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unsigned int cmd_allow, unsigned int vfront, unsigned int vback)
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{
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unsigned int reg;
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reg = (readl(dsim->reg_base + EXYNOS_DSIM_MVPORCH)) &
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~((DSIM_CMD_ALLOW_MASK) | (DSIM_STABLE_VFP_MASK) |
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(DSIM_MAIN_VBP_MASK));
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reg |= (DSIM_CMD_ALLOW_SHIFT(cmd_allow & 0xf) |
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DSIM_STABLE_VFP_SHIFT(vfront & 0x7ff) |
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DSIM_MAIN_VBP_SHIFT(vback & 0x7ff));
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writel(reg, dsim->reg_base + EXYNOS_DSIM_MVPORCH);
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}
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void exynos_mipi_dsi_set_main_disp_hporch(struct mipi_dsim_device *dsim,
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unsigned int front, unsigned int back)
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{
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unsigned int reg;
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reg = (readl(dsim->reg_base + EXYNOS_DSIM_MHPORCH)) &
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~((DSIM_MAIN_HFP_MASK) | (DSIM_MAIN_HBP_MASK));
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reg |= DSIM_MAIN_HFP_SHIFT(front) | DSIM_MAIN_HBP_SHIFT(back);
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writel(reg, dsim->reg_base + EXYNOS_DSIM_MHPORCH);
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}
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void exynos_mipi_dsi_set_main_disp_sync_area(struct mipi_dsim_device *dsim,
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unsigned int vert, unsigned int hori)
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{
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unsigned int reg;
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reg = (readl(dsim->reg_base + EXYNOS_DSIM_MSYNC)) &
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~((DSIM_MAIN_VSA_MASK) | (DSIM_MAIN_HSA_MASK));
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reg |= (DSIM_MAIN_VSA_SHIFT(vert & 0x3ff) |
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DSIM_MAIN_HSA_SHIFT(hori));
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writel(reg, dsim->reg_base + EXYNOS_DSIM_MSYNC);
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}
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void exynos_mipi_dsi_set_sub_disp_resol(struct mipi_dsim_device *dsim,
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unsigned int vert, unsigned int hori)
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{
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unsigned int reg;
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reg = (readl(dsim->reg_base + EXYNOS_DSIM_SDRESOL)) &
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~(DSIM_SUB_STANDY_MASK);
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writel(reg, dsim->reg_base + EXYNOS_DSIM_SDRESOL);
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reg &= ~(DSIM_SUB_VRESOL_MASK) | ~(DSIM_SUB_HRESOL_MASK);
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reg |= (DSIM_SUB_VRESOL_SHIFT(vert & 0x7ff) |
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DSIM_SUB_HRESOL_SHIFT(hori & 0x7ff));
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writel(reg, dsim->reg_base + EXYNOS_DSIM_SDRESOL);
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reg |= DSIM_SUB_STANDY_SHIFT(1);
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writel(reg, dsim->reg_base + EXYNOS_DSIM_SDRESOL);
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}
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void exynos_mipi_dsi_init_config(struct mipi_dsim_device *dsim)
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{
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struct mipi_dsim_config *dsim_config = dsim->dsim_config;
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unsigned int cfg = (readl(dsim->reg_base + EXYNOS_DSIM_CONFIG)) &
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~((1 << 28) | (0x1f << 20) | (0x3 << 5));
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cfg = ((DSIM_AUTO_FLUSH(dsim_config->auto_flush)) |
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(DSIM_EOT_DISABLE(dsim_config->eot_disable)) |
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(DSIM_AUTO_MODE_SHIFT(dsim_config->auto_vertical_cnt)) |
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(DSIM_HSE_MODE_SHIFT(dsim_config->hse)) |
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(DSIM_HFP_MODE_SHIFT(dsim_config->hfp)) |
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(DSIM_HBP_MODE_SHIFT(dsim_config->hbp)) |
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(DSIM_HSA_MODE_SHIFT(dsim_config->hsa)) |
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(DSIM_NUM_OF_DATALANE_SHIFT(dsim_config->e_no_data_lane)));
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writel(cfg, dsim->reg_base + EXYNOS_DSIM_CONFIG);
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}
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void exynos_mipi_dsi_display_config(struct mipi_dsim_device *dsim,
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struct mipi_dsim_config *dsim_config)
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{
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u32 reg = (readl(dsim->reg_base + EXYNOS_DSIM_CONFIG)) &
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~((0x3 << 26) | (1 << 25) | (0x3 << 18) | (0x7 << 12) |
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(0x3 << 16) | (0x7 << 8));
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if (dsim_config->e_interface == DSIM_VIDEO)
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reg |= (1 << 25);
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else if (dsim_config->e_interface == DSIM_COMMAND)
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reg &= ~(1 << 25);
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else {
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dev_err(dsim->dev, "unknown lcd type.\n");
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return;
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}
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/* main lcd */
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reg |= ((u8) (dsim_config->e_burst_mode) & 0x3) << 26 |
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((u8) (dsim_config->e_virtual_ch) & 0x3) << 18 |
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((u8) (dsim_config->e_pixel_format) & 0x7) << 12;
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writel(reg, dsim->reg_base + EXYNOS_DSIM_CONFIG);
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}
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void exynos_mipi_dsi_enable_lane(struct mipi_dsim_device *dsim, unsigned int lane,
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unsigned int enable)
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{
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unsigned int reg;
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reg = readl(dsim->reg_base + EXYNOS_DSIM_CONFIG);
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if (enable)
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reg |= DSIM_LANE_ENx(lane);
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else
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reg &= ~DSIM_LANE_ENx(lane);
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writel(reg, dsim->reg_base + EXYNOS_DSIM_CONFIG);
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}
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void exynos_mipi_dsi_set_data_lane_number(struct mipi_dsim_device *dsim,
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unsigned int count)
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{
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unsigned int cfg;
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/* get the data lane number. */
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cfg = DSIM_NUM_OF_DATALANE_SHIFT(count);
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writel(cfg, dsim->reg_base + EXYNOS_DSIM_CONFIG);
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}
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void exynos_mipi_dsi_enable_afc(struct mipi_dsim_device *dsim, unsigned int enable,
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unsigned int afc_code)
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{
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unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_PHYACCHR);
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if (enable) {
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reg |= (1 << 14);
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reg &= ~(0x7 << 5);
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reg |= (afc_code & 0x7) << 5;
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} else
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reg &= ~(1 << 14);
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writel(reg, dsim->reg_base + EXYNOS_DSIM_PHYACCHR);
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}
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void exynos_mipi_dsi_enable_pll_bypass(struct mipi_dsim_device *dsim,
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unsigned int enable)
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{
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unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) &
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~(DSIM_PLL_BYPASS_SHIFT(0x1));
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reg |= DSIM_PLL_BYPASS_SHIFT(enable);
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writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
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}
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void exynos_mipi_dsi_set_pll_pms(struct mipi_dsim_device *dsim, unsigned int p,
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unsigned int m, unsigned int s)
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{
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unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
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reg |= ((p & 0x3f) << 13) | ((m & 0x1ff) << 4) | ((s & 0x7) << 1);
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writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
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}
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void exynos_mipi_dsi_pll_freq_band(struct mipi_dsim_device *dsim,
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unsigned int freq_band)
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{
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unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) &
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~(DSIM_FREQ_BAND_SHIFT(0x1f));
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reg |= DSIM_FREQ_BAND_SHIFT(freq_band & 0x1f);
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writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
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}
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void exynos_mipi_dsi_pll_freq(struct mipi_dsim_device *dsim,
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unsigned int pre_divider, unsigned int main_divider,
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unsigned int scaler)
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{
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unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) &
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~(0x7ffff << 1);
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reg |= (pre_divider & 0x3f) << 13 | (main_divider & 0x1ff) << 4 |
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(scaler & 0x7) << 1;
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writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
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}
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void exynos_mipi_dsi_pll_stable_time(struct mipi_dsim_device *dsim,
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unsigned int lock_time)
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{
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writel(lock_time, dsim->reg_base + EXYNOS_DSIM_PLLTMR);
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}
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void exynos_mipi_dsi_enable_pll(struct mipi_dsim_device *dsim, unsigned int enable)
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{
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unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) &
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~(DSIM_PLL_EN_SHIFT(0x1));
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reg |= DSIM_PLL_EN_SHIFT(enable & 0x1);
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writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
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}
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void exynos_mipi_dsi_set_byte_clock_src(struct mipi_dsim_device *dsim,
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unsigned int src)
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{
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unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) &
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~(DSIM_BYTE_CLK_SRC_SHIFT(0x3));
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reg |= (DSIM_BYTE_CLK_SRC_SHIFT(src));
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writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
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}
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void exynos_mipi_dsi_enable_byte_clock(struct mipi_dsim_device *dsim,
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unsigned int enable)
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{
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unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) &
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~(DSIM_BYTE_CLKEN_SHIFT(0x1));
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reg |= DSIM_BYTE_CLKEN_SHIFT(enable);
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writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
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}
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void exynos_mipi_dsi_set_esc_clk_prs(struct mipi_dsim_device *dsim,
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unsigned int enable, unsigned int prs_val)
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{
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unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) &
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~(DSIM_ESC_CLKEN_SHIFT(0x1) | 0xffff);
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reg |= DSIM_ESC_CLKEN_SHIFT(enable);
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if (enable)
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reg |= prs_val;
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writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
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}
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void exynos_mipi_dsi_enable_esc_clk_on_lane(struct mipi_dsim_device *dsim,
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unsigned int lane_sel, unsigned int enable)
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{
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unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
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if (enable)
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reg |= DSIM_LANE_ESC_CLKEN(lane_sel);
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else
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reg &= ~DSIM_LANE_ESC_CLKEN(lane_sel);
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writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
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}
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void exynos_mipi_dsi_force_dphy_stop_state(struct mipi_dsim_device *dsim,
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unsigned int enable)
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{
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unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE)) &
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~(DSIM_FORCE_STOP_STATE_SHIFT(0x1));
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reg |= (DSIM_FORCE_STOP_STATE_SHIFT(enable & 0x1));
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writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE);
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}
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unsigned int exynos_mipi_dsi_is_lane_state(struct mipi_dsim_device *dsim)
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{
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unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_STATUS);
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/**
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* check clock and data lane states.
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* if MIPI-DSI controller was enabled at bootloader then
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* TX_READY_HS_CLK is enabled otherwise STOP_STATE_CLK.
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* so it should be checked for two case.
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*/
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if ((reg & DSIM_STOP_STATE_DAT(0xf)) &&
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((reg & DSIM_STOP_STATE_CLK) ||
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(reg & DSIM_TX_READY_HS_CLK)))
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return 1;
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return 0;
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}
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void exynos_mipi_dsi_set_stop_state_counter(struct mipi_dsim_device *dsim,
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unsigned int cnt_val)
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{
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unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE)) &
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~(DSIM_STOP_STATE_CNT_SHIFT(0x7ff));
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reg |= (DSIM_STOP_STATE_CNT_SHIFT(cnt_val & 0x7ff));
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writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE);
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}
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void exynos_mipi_dsi_set_bta_timeout(struct mipi_dsim_device *dsim,
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unsigned int timeout)
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{
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unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_TIMEOUT)) &
|
|
~(DSIM_BTA_TOUT_SHIFT(0xff));
|
|
|
|
reg |= (DSIM_BTA_TOUT_SHIFT(timeout));
|
|
|
|
writel(reg, dsim->reg_base + EXYNOS_DSIM_TIMEOUT);
|
|
}
|
|
|
|
void exynos_mipi_dsi_set_lpdr_timeout(struct mipi_dsim_device *dsim,
|
|
unsigned int timeout)
|
|
{
|
|
unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_TIMEOUT)) &
|
|
~(DSIM_LPDR_TOUT_SHIFT(0xffff));
|
|
|
|
reg |= (DSIM_LPDR_TOUT_SHIFT(timeout));
|
|
|
|
writel(reg, dsim->reg_base + EXYNOS_DSIM_TIMEOUT);
|
|
}
|
|
|
|
void exynos_mipi_dsi_set_cpu_transfer_mode(struct mipi_dsim_device *dsim,
|
|
unsigned int lp)
|
|
{
|
|
unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE);
|
|
|
|
reg &= ~DSIM_CMD_LPDT_LP;
|
|
|
|
if (lp)
|
|
reg |= DSIM_CMD_LPDT_LP;
|
|
|
|
writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE);
|
|
}
|
|
|
|
void exynos_mipi_dsi_set_lcdc_transfer_mode(struct mipi_dsim_device *dsim,
|
|
unsigned int lp)
|
|
{
|
|
unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE);
|
|
|
|
reg &= ~DSIM_TX_LPDT_LP;
|
|
|
|
if (lp)
|
|
reg |= DSIM_TX_LPDT_LP;
|
|
|
|
writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE);
|
|
}
|
|
|
|
void exynos_mipi_dsi_enable_hs_clock(struct mipi_dsim_device *dsim,
|
|
unsigned int enable)
|
|
{
|
|
unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) &
|
|
~(DSIM_TX_REQUEST_HSCLK_SHIFT(0x1));
|
|
|
|
reg |= DSIM_TX_REQUEST_HSCLK_SHIFT(enable);
|
|
|
|
writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
|
|
}
|
|
|
|
void exynos_mipi_dsi_dp_dn_swap(struct mipi_dsim_device *dsim,
|
|
unsigned int swap_en)
|
|
{
|
|
unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_PHYACCHR1);
|
|
|
|
reg &= ~(0x3 << 0);
|
|
reg |= (swap_en & 0x3) << 0;
|
|
|
|
writel(reg, dsim->reg_base + EXYNOS_DSIM_PHYACCHR1);
|
|
}
|
|
|
|
void exynos_mipi_dsi_hs_zero_ctrl(struct mipi_dsim_device *dsim,
|
|
unsigned int hs_zero)
|
|
{
|
|
unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) &
|
|
~(0xf << 28);
|
|
|
|
reg |= ((hs_zero & 0xf) << 28);
|
|
|
|
writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
|
|
}
|
|
|
|
void exynos_mipi_dsi_prep_ctrl(struct mipi_dsim_device *dsim, unsigned int prep)
|
|
{
|
|
unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) &
|
|
~(0x7 << 20);
|
|
|
|
reg |= ((prep & 0x7) << 20);
|
|
|
|
writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
|
|
}
|
|
|
|
unsigned int exynos_mipi_dsi_read_interrupt(struct mipi_dsim_device *dsim)
|
|
{
|
|
return readl(dsim->reg_base + EXYNOS_DSIM_INTSRC);
|
|
}
|
|
|
|
void exynos_mipi_dsi_clear_interrupt(struct mipi_dsim_device *dsim,
|
|
unsigned int src)
|
|
{
|
|
unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC);
|
|
|
|
reg |= src;
|
|
|
|
writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC);
|
|
}
|
|
|
|
void exynos_mipi_dsi_set_interrupt(struct mipi_dsim_device *dsim,
|
|
unsigned int src, unsigned int enable)
|
|
{
|
|
unsigned int reg = 0;
|
|
|
|
if (enable)
|
|
reg |= src;
|
|
else
|
|
reg &= ~src;
|
|
|
|
writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC);
|
|
}
|
|
|
|
unsigned int exynos_mipi_dsi_is_pll_stable(struct mipi_dsim_device *dsim)
|
|
{
|
|
unsigned int reg;
|
|
|
|
reg = readl(dsim->reg_base + EXYNOS_DSIM_STATUS);
|
|
|
|
return reg & (1 << 31) ? 1 : 0;
|
|
}
|
|
|
|
unsigned int exynos_mipi_dsi_get_fifo_state(struct mipi_dsim_device *dsim)
|
|
{
|
|
return readl(dsim->reg_base + EXYNOS_DSIM_FIFOCTRL) & ~(0x1f);
|
|
}
|
|
|
|
void exynos_mipi_dsi_wr_tx_header(struct mipi_dsim_device *dsim,
|
|
unsigned int di, unsigned int data0, unsigned int data1)
|
|
{
|
|
unsigned int reg = (data1 << 16) | (data0 << 8) | ((di & 0x3f) << 0);
|
|
|
|
writel(reg, dsim->reg_base + EXYNOS_DSIM_PKTHDR);
|
|
}
|
|
|
|
void exynos_mipi_dsi_rd_tx_header(struct mipi_dsim_device *dsim,
|
|
unsigned int di, unsigned int data0)
|
|
{
|
|
unsigned int reg = (data0 << 8) | (di << 0);
|
|
|
|
writel(reg, dsim->reg_base + EXYNOS_DSIM_PKTHDR);
|
|
}
|
|
|
|
unsigned int exynos_mipi_dsi_rd_rx_fifo(struct mipi_dsim_device *dsim)
|
|
{
|
|
return readl(dsim->reg_base + EXYNOS_DSIM_RXFIFO);
|
|
}
|
|
|
|
unsigned int _exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim)
|
|
{
|
|
unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC);
|
|
|
|
return (reg & INTSRC_FRAME_DONE) ? 1 : 0;
|
|
}
|
|
|
|
void _exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim)
|
|
{
|
|
unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC);
|
|
|
|
writel(reg | INTSRC_FRAME_DONE, dsim->reg_base +
|
|
EXYNOS_DSIM_INTSRC);
|
|
}
|
|
|
|
void exynos_mipi_dsi_wr_tx_data(struct mipi_dsim_device *dsim,
|
|
unsigned int tx_data)
|
|
{
|
|
writel(tx_data, dsim->reg_base + EXYNOS_DSIM_PAYLOAD);
|
|
}
|