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a5841de691
Add the clkids for the clocks feeding the input0 of the mmc controllers Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
118 lines
2.9 KiB
C
118 lines
2.9 KiB
C
/*
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* GXBB clock tree IDs
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*/
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#ifndef __GXBB_CLKC_H
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#define __GXBB_CLKC_H
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#define CLKID_SYS_PLL 0
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#define CLKID_HDMI_PLL 2
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#define CLKID_FIXED_PLL 3
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#define CLKID_FCLK_DIV2 4
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#define CLKID_FCLK_DIV3 5
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#define CLKID_FCLK_DIV4 6
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#define CLKID_FCLK_DIV5 7
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#define CLKID_FCLK_DIV7 8
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#define CLKID_GP0_PLL 9
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#define CLKID_CLK81 12
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#define CLKID_MPLL0 13
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#define CLKID_MPLL1 14
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#define CLKID_MPLL2 15
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#define CLKID_DDR 16
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#define CLKID_DOS 17
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#define CLKID_ISA 18
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#define CLKID_PL301 19
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#define CLKID_PERIPHS 20
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#define CLKID_SPICC 21
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#define CLKID_I2C 22
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#define CLKID_SAR_ADC 23
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#define CLKID_SMART_CARD 24
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#define CLKID_RNG0 25
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#define CLKID_UART0 26
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#define CLKID_SDHC 27
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#define CLKID_STREAM 28
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#define CLKID_ASYNC_FIFO 29
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#define CLKID_SDIO 30
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#define CLKID_ABUF 31
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#define CLKID_HIU_IFACE 32
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#define CLKID_ASSIST_MISC 33
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#define CLKID_SPI 34
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#define CLKID_ETH 36
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#define CLKID_I2S_SPDIF 35
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#define CLKID_DEMUX 37
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#define CLKID_AIU_GLUE 38
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#define CLKID_IEC958 39
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#define CLKID_I2S_OUT 40
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#define CLKID_AMCLK 41
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#define CLKID_AIFIFO2 42
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#define CLKID_MIXER 43
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#define CLKID_MIXER_IFACE 44
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#define CLKID_ADC 45
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#define CLKID_BLKMV 46
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#define CLKID_AIU 47
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#define CLKID_UART1 48
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#define CLKID_G2D 49
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#define CLKID_USB0 50
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#define CLKID_USB1 51
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#define CLKID_RESET 52
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#define CLKID_NAND 53
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#define CLKID_DOS_PARSER 54
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#define CLKID_USB 55
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#define CLKID_VDIN1 56
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#define CLKID_AHB_ARB0 57
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#define CLKID_EFUSE 58
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#define CLKID_BOOT_ROM 59
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#define CLKID_AHB_DATA_BUS 60
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#define CLKID_AHB_CTRL_BUS 61
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#define CLKID_HDMI_INTR_SYNC 62
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#define CLKID_HDMI_PCLK 63
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#define CLKID_USB1_DDR_BRIDGE 64
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#define CLKID_USB0_DDR_BRIDGE 65
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#define CLKID_MMC_PCLK 66
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#define CLKID_DVIN 67
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#define CLKID_UART2 68
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#define CLKID_SANA 69
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#define CLKID_VPU_INTR 70
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#define CLKID_SEC_AHB_AHB3_BRIDGE 71
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#define CLKID_CLK81_A53 72
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#define CLKID_VCLK2_VENCI0 73
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#define CLKID_VCLK2_VENCI1 74
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#define CLKID_VCLK2_VENCP0 75
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#define CLKID_VCLK2_VENCP1 76
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#define CLKID_GCLK_VENCI_INT0 77
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#define CLKID_GCLK_VENCI_INT 78
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#define CLKID_DAC_CLK 79
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#define CLKID_AOCLK_GATE 80
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#define CLKID_IEC958_GATE 81
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#define CLKID_ENC480P 82
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#define CLKID_RNG1 83
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#define CLKID_GCLK_VENCI_INT1 84
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#define CLKID_VCLK2_VENCLMCC 85
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#define CLKID_VCLK2_VENCL 86
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#define CLKID_VCLK_OTHER 87
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#define CLKID_EDP 88
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#define CLKID_AO_MEDIA_CPU 89
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#define CLKID_AO_AHB_SRAM 90
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#define CLKID_AO_AHB_BUS 91
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#define CLKID_AO_IFACE 92
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#define CLKID_AO_I2C 93
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#define CLKID_SD_EMMC_A 94
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#define CLKID_SD_EMMC_B 95
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#define CLKID_SD_EMMC_C 96
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#define CLKID_SAR_ADC_CLK 97
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#define CLKID_SAR_ADC_SEL 98
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#define CLKID_MALI_0_SEL 100
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#define CLKID_MALI_0 102
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#define CLKID_MALI_1_SEL 103
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#define CLKID_MALI_1 105
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#define CLKID_MALI 106
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#define CLKID_CTS_AMCLK 107
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#define CLKID_CTS_MCLK_I958 110
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#define CLKID_CTS_I958 113
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#define CLKID_32K_CLK 114
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#define CLKID_SD_EMMC_A_CLK0 119
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#define CLKID_SD_EMMC_B_CLK0 122
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#define CLKID_SD_EMMC_C_CLK0 125
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#endif /* __GXBB_CLKC_H */
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