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d223f98f02
The compute shader dispatch interface is pretty simple -- just pass in
the regs that userspace has passed us, with no CLs to run. However,
with no CL to run it means that we need to do manual cache flushing of
the L2 after the HW execution completes (for SSBO, atomic, and
image_load_store writes that are the output of compute shaders).
This doesn't yet expose the L2 cache's ability to have a region of the
address space not write back to memory (which could be used for
shared_var storage).
So far, the Mesa side has been tested on V3D v4.2 simpenrose (passing
the ES31 tests), and on the kernel side on 7278 (failing atomic
compswap tests in a way that doesn't reproduce on simpenrose).
v2: Fix excessive allocation for the clean_job (reported by Dan
Carpenter). Keep refs on jobs until clean_job is finished, to
avoid spurious MMU errors if the output BOs are freed by userspace
before L2 cleaning is finished.
Signed-off-by: Eric Anholt <eric@anholt.net>
Link: https://patchwork.freedesktop.org/patch/msgid/20190416225856.20264-4-eric@anholt.net
Acked-by: Rob Clark <robdclark@gmail.com>
298 lines
6.0 KiB
C
298 lines
6.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/* Copyright (C) 2015-2018 Broadcom */
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#if !defined(_V3D_TRACE_H_) || defined(TRACE_HEADER_MULTI_READ)
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#define _V3D_TRACE_H_
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#include <linux/stringify.h>
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#include <linux/types.h>
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#include <linux/tracepoint.h>
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#undef TRACE_SYSTEM
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#define TRACE_SYSTEM v3d
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#define TRACE_INCLUDE_FILE v3d_trace
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TRACE_EVENT(v3d_submit_cl_ioctl,
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TP_PROTO(struct drm_device *dev, u32 ct1qba, u32 ct1qea),
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TP_ARGS(dev, ct1qba, ct1qea),
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TP_STRUCT__entry(
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__field(u32, dev)
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__field(u32, ct1qba)
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__field(u32, ct1qea)
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),
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TP_fast_assign(
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__entry->dev = dev->primary->index;
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__entry->ct1qba = ct1qba;
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__entry->ct1qea = ct1qea;
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),
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TP_printk("dev=%u, RCL 0x%08x..0x%08x",
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__entry->dev,
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__entry->ct1qba,
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__entry->ct1qea)
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);
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TRACE_EVENT(v3d_submit_cl,
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TP_PROTO(struct drm_device *dev, bool is_render,
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uint64_t seqno,
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u32 ctnqba, u32 ctnqea),
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TP_ARGS(dev, is_render, seqno, ctnqba, ctnqea),
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TP_STRUCT__entry(
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__field(u32, dev)
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__field(bool, is_render)
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__field(u64, seqno)
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__field(u32, ctnqba)
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__field(u32, ctnqea)
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),
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TP_fast_assign(
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__entry->dev = dev->primary->index;
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__entry->is_render = is_render;
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__entry->seqno = seqno;
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__entry->ctnqba = ctnqba;
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__entry->ctnqea = ctnqea;
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),
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TP_printk("dev=%u, %s, seqno=%llu, 0x%08x..0x%08x",
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__entry->dev,
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__entry->is_render ? "RCL" : "BCL",
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__entry->seqno,
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__entry->ctnqba,
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__entry->ctnqea)
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);
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TRACE_EVENT(v3d_bcl_irq,
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TP_PROTO(struct drm_device *dev,
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uint64_t seqno),
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TP_ARGS(dev, seqno),
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TP_STRUCT__entry(
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__field(u32, dev)
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__field(u64, seqno)
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),
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TP_fast_assign(
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__entry->dev = dev->primary->index;
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__entry->seqno = seqno;
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),
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TP_printk("dev=%u, seqno=%llu",
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__entry->dev,
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__entry->seqno)
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);
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TRACE_EVENT(v3d_rcl_irq,
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TP_PROTO(struct drm_device *dev,
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uint64_t seqno),
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TP_ARGS(dev, seqno),
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TP_STRUCT__entry(
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__field(u32, dev)
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__field(u64, seqno)
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),
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TP_fast_assign(
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__entry->dev = dev->primary->index;
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__entry->seqno = seqno;
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),
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TP_printk("dev=%u, seqno=%llu",
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__entry->dev,
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__entry->seqno)
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);
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TRACE_EVENT(v3d_tfu_irq,
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TP_PROTO(struct drm_device *dev,
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uint64_t seqno),
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TP_ARGS(dev, seqno),
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TP_STRUCT__entry(
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__field(u32, dev)
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__field(u64, seqno)
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),
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TP_fast_assign(
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__entry->dev = dev->primary->index;
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__entry->seqno = seqno;
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),
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TP_printk("dev=%u, seqno=%llu",
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__entry->dev,
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__entry->seqno)
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);
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TRACE_EVENT(v3d_csd_irq,
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TP_PROTO(struct drm_device *dev,
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uint64_t seqno),
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TP_ARGS(dev, seqno),
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TP_STRUCT__entry(
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__field(u32, dev)
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__field(u64, seqno)
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),
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TP_fast_assign(
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__entry->dev = dev->primary->index;
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__entry->seqno = seqno;
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),
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TP_printk("dev=%u, seqno=%llu",
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__entry->dev,
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__entry->seqno)
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);
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TRACE_EVENT(v3d_submit_tfu_ioctl,
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TP_PROTO(struct drm_device *dev, u32 iia),
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TP_ARGS(dev, iia),
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TP_STRUCT__entry(
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__field(u32, dev)
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__field(u32, iia)
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),
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TP_fast_assign(
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__entry->dev = dev->primary->index;
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__entry->iia = iia;
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),
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TP_printk("dev=%u, IIA 0x%08x",
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__entry->dev,
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__entry->iia)
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);
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TRACE_EVENT(v3d_submit_tfu,
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TP_PROTO(struct drm_device *dev,
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uint64_t seqno),
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TP_ARGS(dev, seqno),
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TP_STRUCT__entry(
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__field(u32, dev)
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__field(u64, seqno)
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),
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TP_fast_assign(
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__entry->dev = dev->primary->index;
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__entry->seqno = seqno;
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),
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TP_printk("dev=%u, seqno=%llu",
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__entry->dev,
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__entry->seqno)
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);
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TRACE_EVENT(v3d_submit_csd_ioctl,
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TP_PROTO(struct drm_device *dev, u32 cfg5, u32 cfg6),
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TP_ARGS(dev, cfg5, cfg6),
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TP_STRUCT__entry(
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__field(u32, dev)
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__field(u32, cfg5)
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__field(u32, cfg6)
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),
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TP_fast_assign(
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__entry->dev = dev->primary->index;
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__entry->cfg5 = cfg5;
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__entry->cfg6 = cfg6;
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),
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TP_printk("dev=%u, CFG5 0x%08x, CFG6 0x%08x",
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__entry->dev,
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__entry->cfg5,
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__entry->cfg6)
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);
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TRACE_EVENT(v3d_submit_csd,
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TP_PROTO(struct drm_device *dev,
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uint64_t seqno),
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TP_ARGS(dev, seqno),
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TP_STRUCT__entry(
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__field(u32, dev)
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__field(u64, seqno)
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),
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TP_fast_assign(
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__entry->dev = dev->primary->index;
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__entry->seqno = seqno;
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),
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TP_printk("dev=%u, seqno=%llu",
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__entry->dev,
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__entry->seqno)
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);
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TRACE_EVENT(v3d_cache_clean_begin,
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TP_PROTO(struct drm_device *dev),
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TP_ARGS(dev),
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TP_STRUCT__entry(
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__field(u32, dev)
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),
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TP_fast_assign(
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__entry->dev = dev->primary->index;
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),
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TP_printk("dev=%u",
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__entry->dev)
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);
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TRACE_EVENT(v3d_cache_clean_end,
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TP_PROTO(struct drm_device *dev),
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TP_ARGS(dev),
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TP_STRUCT__entry(
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__field(u32, dev)
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),
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TP_fast_assign(
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__entry->dev = dev->primary->index;
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),
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TP_printk("dev=%u",
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__entry->dev)
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);
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TRACE_EVENT(v3d_reset_begin,
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TP_PROTO(struct drm_device *dev),
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TP_ARGS(dev),
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TP_STRUCT__entry(
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__field(u32, dev)
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),
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TP_fast_assign(
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__entry->dev = dev->primary->index;
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),
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TP_printk("dev=%u",
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__entry->dev)
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);
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TRACE_EVENT(v3d_reset_end,
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TP_PROTO(struct drm_device *dev),
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TP_ARGS(dev),
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TP_STRUCT__entry(
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__field(u32, dev)
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),
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TP_fast_assign(
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__entry->dev = dev->primary->index;
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),
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TP_printk("dev=%u",
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__entry->dev)
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);
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#endif /* _V3D_TRACE_H_ */
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/* This part must be outside protection */
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#undef TRACE_INCLUDE_PATH
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#define TRACE_INCLUDE_PATH .
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#include <trace/define_trace.h>
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