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d4f3388afd
Add support to specify platform specific transition_delay_us instead of using the transition delay derived from PCC. With commit3d41386d55
(cpufreq: CPPC: Use transition_delay_us depending transition_latency) we are setting transition_delay_us directly and not applying the LATENCY_MULTIPLIER. Because of that, on Qualcomm Centriq we can end up with a very high rate of frequency change requests when using the schedutil governor (default rate_limit_us=10 compared to an earlier value of 10000). The PCC subspace describes the rate at which the platform can accept commands on the CPPC's PCC channel. This includes read and write command on the PCC channel that can be used for reasons other than frequency transitions. Moreover the same PCC subspace can be used by multiple freq domains and deriving transition_delay_us from it as we do now can be sub-optimal. Moreover if a platform does not use PCC for desired_perf register then there is no way to compute the transition latency or the delay_us. CPPC does not have a standard defined mechanism to get the transition rate or the latency at the moment. Given the above limitations, it is simpler to have a platform specific transition_delay_us and rely on PCC derived value only if a platform specific value is not available. Signed-off-by: Prashanth Prakash <pprakash@codeaurora.org> Cc: 4.14+ <stable@vger.kernel.org> # 4.14+ Fixes:3d41386d55
(cpufreq: CPPC: Use transition_delay_us depending transition_latency) Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
328 lines
7.9 KiB
C
328 lines
7.9 KiB
C
/*
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* CPPC (Collaborative Processor Performance Control) driver for
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* interfacing with the CPUfreq layer and governors. See
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* cppc_acpi.c for CPPC specific methods.
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*
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* (C) Copyright 2014, 2015 Linaro Ltd.
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* Author: Ashwin Chaugule <ashwin.chaugule@linaro.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2
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* of the License.
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*/
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#define pr_fmt(fmt) "CPPC Cpufreq:" fmt
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/cpu.h>
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#include <linux/cpufreq.h>
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#include <linux/dmi.h>
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#include <linux/time.h>
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#include <linux/vmalloc.h>
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#include <asm/unaligned.h>
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#include <acpi/cppc_acpi.h>
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/* Minimum struct length needed for the DMI processor entry we want */
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#define DMI_ENTRY_PROCESSOR_MIN_LENGTH 48
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/* Offest in the DMI processor structure for the max frequency */
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#define DMI_PROCESSOR_MAX_SPEED 0x14
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/*
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* These structs contain information parsed from per CPU
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* ACPI _CPC structures.
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* e.g. For each CPU the highest, lowest supported
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* performance capabilities, desired performance level
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* requested etc.
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*/
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static struct cppc_cpudata **all_cpu_data;
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/* Capture the max KHz from DMI */
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static u64 cppc_dmi_max_khz;
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/* Callback function used to retrieve the max frequency from DMI */
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static void cppc_find_dmi_mhz(const struct dmi_header *dm, void *private)
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{
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const u8 *dmi_data = (const u8 *)dm;
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u16 *mhz = (u16 *)private;
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if (dm->type == DMI_ENTRY_PROCESSOR &&
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dm->length >= DMI_ENTRY_PROCESSOR_MIN_LENGTH) {
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u16 val = (u16)get_unaligned((const u16 *)
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(dmi_data + DMI_PROCESSOR_MAX_SPEED));
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*mhz = val > *mhz ? val : *mhz;
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}
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}
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/* Look up the max frequency in DMI */
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static u64 cppc_get_dmi_max_khz(void)
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{
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u16 mhz = 0;
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dmi_walk(cppc_find_dmi_mhz, &mhz);
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/*
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* Real stupid fallback value, just in case there is no
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* actual value set.
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*/
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mhz = mhz ? mhz : 1;
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return (1000 * mhz);
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}
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static int cppc_cpufreq_set_target(struct cpufreq_policy *policy,
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unsigned int target_freq,
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unsigned int relation)
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{
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struct cppc_cpudata *cpu;
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struct cpufreq_freqs freqs;
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u32 desired_perf;
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int ret = 0;
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cpu = all_cpu_data[policy->cpu];
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desired_perf = (u64)target_freq * cpu->perf_caps.highest_perf / cppc_dmi_max_khz;
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/* Return if it is exactly the same perf */
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if (desired_perf == cpu->perf_ctrls.desired_perf)
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return ret;
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cpu->perf_ctrls.desired_perf = desired_perf;
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freqs.old = policy->cur;
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freqs.new = target_freq;
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cpufreq_freq_transition_begin(policy, &freqs);
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ret = cppc_set_perf(cpu->cpu, &cpu->perf_ctrls);
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cpufreq_freq_transition_end(policy, &freqs, ret != 0);
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if (ret)
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pr_debug("Failed to set target on CPU:%d. ret:%d\n",
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cpu->cpu, ret);
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return ret;
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}
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static int cppc_verify_policy(struct cpufreq_policy *policy)
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{
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cpufreq_verify_within_cpu_limits(policy);
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return 0;
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}
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static void cppc_cpufreq_stop_cpu(struct cpufreq_policy *policy)
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{
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int cpu_num = policy->cpu;
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struct cppc_cpudata *cpu = all_cpu_data[cpu_num];
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int ret;
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cpu->perf_ctrls.desired_perf = cpu->perf_caps.lowest_perf;
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ret = cppc_set_perf(cpu_num, &cpu->perf_ctrls);
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if (ret)
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pr_debug("Err setting perf value:%d on CPU:%d. ret:%d\n",
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cpu->perf_caps.lowest_perf, cpu_num, ret);
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}
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/*
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* The PCC subspace describes the rate at which platform can accept commands
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* on the shared PCC channel (including READs which do not count towards freq
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* trasition requests), so ideally we need to use the PCC values as a fallback
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* if we don't have a platform specific transition_delay_us
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*/
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#ifdef CONFIG_ARM64
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#include <asm/cputype.h>
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static unsigned int cppc_cpufreq_get_transition_delay_us(int cpu)
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{
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unsigned long implementor = read_cpuid_implementor();
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unsigned long part_num = read_cpuid_part_number();
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unsigned int delay_us = 0;
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switch (implementor) {
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case ARM_CPU_IMP_QCOM:
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switch (part_num) {
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case QCOM_CPU_PART_FALKOR_V1:
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case QCOM_CPU_PART_FALKOR:
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delay_us = 10000;
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break;
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default:
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delay_us = cppc_get_transition_latency(cpu) / NSEC_PER_USEC;
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break;
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}
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break;
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default:
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delay_us = cppc_get_transition_latency(cpu) / NSEC_PER_USEC;
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break;
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}
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return delay_us;
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}
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#else
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static unsigned int cppc_cpufreq_get_transition_delay_us(int cpu)
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{
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return cppc_get_transition_latency(cpu) / NSEC_PER_USEC;
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}
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#endif
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static int cppc_cpufreq_cpu_init(struct cpufreq_policy *policy)
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{
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struct cppc_cpudata *cpu;
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unsigned int cpu_num = policy->cpu;
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int ret = 0;
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cpu = all_cpu_data[policy->cpu];
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cpu->cpu = cpu_num;
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ret = cppc_get_perf_caps(policy->cpu, &cpu->perf_caps);
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if (ret) {
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pr_debug("Err reading CPU%d perf capabilities. ret:%d\n",
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cpu_num, ret);
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return ret;
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}
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cppc_dmi_max_khz = cppc_get_dmi_max_khz();
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/*
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* Set min to lowest nonlinear perf to avoid any efficiency penalty (see
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* Section 8.4.7.1.1.5 of ACPI 6.1 spec)
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*/
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policy->min = cpu->perf_caps.lowest_nonlinear_perf * cppc_dmi_max_khz /
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cpu->perf_caps.highest_perf;
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policy->max = cppc_dmi_max_khz;
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/*
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* Set cpuinfo.min_freq to Lowest to make the full range of performance
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* available if userspace wants to use any perf between lowest & lowest
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* nonlinear perf
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*/
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policy->cpuinfo.min_freq = cpu->perf_caps.lowest_perf * cppc_dmi_max_khz /
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cpu->perf_caps.highest_perf;
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policy->cpuinfo.max_freq = cppc_dmi_max_khz;
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policy->transition_delay_us = cppc_cpufreq_get_transition_delay_us(cpu_num);
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policy->shared_type = cpu->shared_type;
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if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY) {
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int i;
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cpumask_copy(policy->cpus, cpu->shared_cpu_map);
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for_each_cpu(i, policy->cpus) {
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if (unlikely(i == policy->cpu))
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continue;
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memcpy(&all_cpu_data[i]->perf_caps, &cpu->perf_caps,
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sizeof(cpu->perf_caps));
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}
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} else if (policy->shared_type == CPUFREQ_SHARED_TYPE_ALL) {
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/* Support only SW_ANY for now. */
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pr_debug("Unsupported CPU co-ord type\n");
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return -EFAULT;
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}
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cpu->cur_policy = policy;
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/* Set policy->cur to max now. The governors will adjust later. */
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policy->cur = cppc_dmi_max_khz;
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cpu->perf_ctrls.desired_perf = cpu->perf_caps.highest_perf;
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ret = cppc_set_perf(cpu_num, &cpu->perf_ctrls);
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if (ret)
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pr_debug("Err setting perf value:%d on CPU:%d. ret:%d\n",
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cpu->perf_caps.highest_perf, cpu_num, ret);
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return ret;
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}
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static struct cpufreq_driver cppc_cpufreq_driver = {
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.flags = CPUFREQ_CONST_LOOPS,
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.verify = cppc_verify_policy,
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.target = cppc_cpufreq_set_target,
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.init = cppc_cpufreq_cpu_init,
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.stop_cpu = cppc_cpufreq_stop_cpu,
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.name = "cppc_cpufreq",
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};
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static int __init cppc_cpufreq_init(void)
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{
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int i, ret = 0;
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struct cppc_cpudata *cpu;
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if (acpi_disabled)
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return -ENODEV;
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all_cpu_data = kzalloc(sizeof(void *) * num_possible_cpus(), GFP_KERNEL);
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if (!all_cpu_data)
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return -ENOMEM;
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for_each_possible_cpu(i) {
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all_cpu_data[i] = kzalloc(sizeof(struct cppc_cpudata), GFP_KERNEL);
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if (!all_cpu_data[i])
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goto out;
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cpu = all_cpu_data[i];
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if (!zalloc_cpumask_var(&cpu->shared_cpu_map, GFP_KERNEL))
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goto out;
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}
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ret = acpi_get_psd_map(all_cpu_data);
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if (ret) {
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pr_debug("Error parsing PSD data. Aborting cpufreq registration.\n");
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goto out;
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}
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ret = cpufreq_register_driver(&cppc_cpufreq_driver);
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if (ret)
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goto out;
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return ret;
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out:
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for_each_possible_cpu(i) {
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cpu = all_cpu_data[i];
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if (!cpu)
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break;
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free_cpumask_var(cpu->shared_cpu_map);
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kfree(cpu);
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}
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kfree(all_cpu_data);
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return -ENODEV;
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}
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static void __exit cppc_cpufreq_exit(void)
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{
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struct cppc_cpudata *cpu;
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int i;
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cpufreq_unregister_driver(&cppc_cpufreq_driver);
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for_each_possible_cpu(i) {
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cpu = all_cpu_data[i];
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free_cpumask_var(cpu->shared_cpu_map);
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kfree(cpu);
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}
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kfree(all_cpu_data);
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}
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module_exit(cppc_cpufreq_exit);
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MODULE_AUTHOR("Ashwin Chaugule");
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MODULE_DESCRIPTION("CPUFreq driver based on the ACPI CPPC v5.0+ spec");
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MODULE_LICENSE("GPL");
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late_initcall(cppc_cpufreq_init);
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static const struct acpi_device_id cppc_acpi_ids[] = {
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{ACPI_PROCESSOR_DEVICE_HID, },
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{}
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};
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MODULE_DEVICE_TABLE(acpi, cppc_acpi_ids);
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