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e756e932a3
TREX D Core and P core clocks seem to be related to the BTS (Bus Traffic Shaper) inside the Exynos7885 SoC, and are needed for the SoC to function correctly. Add indices for these clocks. Signed-off-by: David Virag <virag.david003@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220601233743.56317-3-virag.david003@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
152 lines
4.6 KiB
C
152 lines
4.6 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2021 Dávid Virág
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*
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* Device Tree binding constants for Exynos7885 clock controller.
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*/
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#ifndef _DT_BINDINGS_CLOCK_EXYNOS_7885_H
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#define _DT_BINDINGS_CLOCK_EXYNOS_7885_H
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/* CMU_TOP */
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#define CLK_FOUT_SHARED0_PLL 1
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#define CLK_FOUT_SHARED1_PLL 2
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#define CLK_DOUT_SHARED0_DIV2 3
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#define CLK_DOUT_SHARED0_DIV3 4
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#define CLK_DOUT_SHARED0_DIV4 5
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#define CLK_DOUT_SHARED0_DIV5 6
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#define CLK_DOUT_SHARED1_DIV2 7
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#define CLK_DOUT_SHARED1_DIV3 8
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#define CLK_DOUT_SHARED1_DIV4 9
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#define CLK_MOUT_CORE_BUS 10
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#define CLK_MOUT_CORE_CCI 11
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#define CLK_MOUT_CORE_G3D 12
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#define CLK_DOUT_CORE_BUS 13
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#define CLK_DOUT_CORE_CCI 14
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#define CLK_DOUT_CORE_G3D 15
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#define CLK_GOUT_CORE_BUS 16
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#define CLK_GOUT_CORE_CCI 17
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#define CLK_GOUT_CORE_G3D 18
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#define CLK_MOUT_PERI_BUS 19
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#define CLK_MOUT_PERI_SPI0 20
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#define CLK_MOUT_PERI_SPI1 21
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#define CLK_MOUT_PERI_UART0 22
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#define CLK_MOUT_PERI_UART1 23
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#define CLK_MOUT_PERI_UART2 24
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#define CLK_MOUT_PERI_USI0 25
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#define CLK_MOUT_PERI_USI1 26
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#define CLK_MOUT_PERI_USI2 27
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#define CLK_DOUT_PERI_BUS 28
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#define CLK_DOUT_PERI_SPI0 29
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#define CLK_DOUT_PERI_SPI1 30
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#define CLK_DOUT_PERI_UART0 31
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#define CLK_DOUT_PERI_UART1 32
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#define CLK_DOUT_PERI_UART2 33
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#define CLK_DOUT_PERI_USI0 34
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#define CLK_DOUT_PERI_USI1 35
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#define CLK_DOUT_PERI_USI2 36
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#define CLK_GOUT_PERI_BUS 37
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#define CLK_GOUT_PERI_SPI0 38
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#define CLK_GOUT_PERI_SPI1 39
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#define CLK_GOUT_PERI_UART0 40
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#define CLK_GOUT_PERI_UART1 41
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#define CLK_GOUT_PERI_UART2 42
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#define CLK_GOUT_PERI_USI0 43
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#define CLK_GOUT_PERI_USI1 44
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#define CLK_GOUT_PERI_USI2 45
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#define CLK_MOUT_FSYS_BUS 46
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#define CLK_MOUT_FSYS_MMC_CARD 47
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#define CLK_MOUT_FSYS_MMC_EMBD 48
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#define CLK_MOUT_FSYS_MMC_SDIO 49
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#define CLK_MOUT_FSYS_USB30DRD 50
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#define CLK_DOUT_FSYS_BUS 51
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#define CLK_DOUT_FSYS_MMC_CARD 52
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#define CLK_DOUT_FSYS_MMC_EMBD 53
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#define CLK_DOUT_FSYS_MMC_SDIO 54
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#define CLK_DOUT_FSYS_USB30DRD 55
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#define CLK_GOUT_FSYS_BUS 56
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#define CLK_GOUT_FSYS_MMC_CARD 57
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#define CLK_GOUT_FSYS_MMC_EMBD 58
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#define CLK_GOUT_FSYS_MMC_SDIO 59
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#define CLK_GOUT_FSYS_USB30DRD 60
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#define TOP_NR_CLK 61
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/* CMU_CORE */
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#define CLK_MOUT_CORE_BUS_USER 1
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#define CLK_MOUT_CORE_CCI_USER 2
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#define CLK_MOUT_CORE_G3D_USER 3
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#define CLK_MOUT_CORE_GIC 4
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#define CLK_DOUT_CORE_BUSP 5
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#define CLK_GOUT_CCI_ACLK 6
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#define CLK_GOUT_GIC400_CLK 7
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#define CLK_GOUT_TREX_D_CORE_ACLK 8
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#define CLK_GOUT_TREX_D_CORE_GCLK 9
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#define CLK_GOUT_TREX_D_CORE_PCLK 10
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#define CLK_GOUT_TREX_P_CORE_ACLK_P_CORE 11
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#define CLK_GOUT_TREX_P_CORE_CCLK_P_CORE 12
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#define CLK_GOUT_TREX_P_CORE_PCLK 13
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#define CLK_GOUT_TREX_P_CORE_PCLK_P_CORE 14
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#define CORE_NR_CLK 15
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/* CMU_PERI */
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#define CLK_MOUT_PERI_BUS_USER 1
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#define CLK_MOUT_PERI_SPI0_USER 2
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#define CLK_MOUT_PERI_SPI1_USER 3
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#define CLK_MOUT_PERI_UART0_USER 4
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#define CLK_MOUT_PERI_UART1_USER 5
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#define CLK_MOUT_PERI_UART2_USER 6
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#define CLK_MOUT_PERI_USI0_USER 7
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#define CLK_MOUT_PERI_USI1_USER 8
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#define CLK_MOUT_PERI_USI2_USER 9
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#define CLK_GOUT_GPIO_TOP_PCLK 10
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#define CLK_GOUT_HSI2C0_PCLK 11
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#define CLK_GOUT_HSI2C1_PCLK 12
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#define CLK_GOUT_HSI2C2_PCLK 13
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#define CLK_GOUT_HSI2C3_PCLK 14
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#define CLK_GOUT_I2C0_PCLK 15
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#define CLK_GOUT_I2C1_PCLK 16
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#define CLK_GOUT_I2C2_PCLK 17
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#define CLK_GOUT_I2C3_PCLK 18
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#define CLK_GOUT_I2C4_PCLK 19
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#define CLK_GOUT_I2C5_PCLK 20
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#define CLK_GOUT_I2C6_PCLK 21
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#define CLK_GOUT_I2C7_PCLK 22
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#define CLK_GOUT_PWM_MOTOR_PCLK 23
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#define CLK_GOUT_SPI0_PCLK 24
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#define CLK_GOUT_SPI0_EXT_CLK 25
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#define CLK_GOUT_SPI1_PCLK 26
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#define CLK_GOUT_SPI1_EXT_CLK 27
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#define CLK_GOUT_UART0_EXT_UCLK 28
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#define CLK_GOUT_UART0_PCLK 29
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#define CLK_GOUT_UART1_EXT_UCLK 30
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#define CLK_GOUT_UART1_PCLK 31
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#define CLK_GOUT_UART2_EXT_UCLK 32
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#define CLK_GOUT_UART2_PCLK 33
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#define CLK_GOUT_USI0_PCLK 34
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#define CLK_GOUT_USI0_SCLK 35
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#define CLK_GOUT_USI1_PCLK 36
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#define CLK_GOUT_USI1_SCLK 37
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#define CLK_GOUT_USI2_PCLK 38
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#define CLK_GOUT_USI2_SCLK 39
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#define CLK_GOUT_MCT_PCLK 40
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#define CLK_GOUT_SYSREG_PERI_PCLK 41
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#define CLK_GOUT_WDT0_PCLK 42
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#define CLK_GOUT_WDT1_PCLK 43
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#define PERI_NR_CLK 44
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/* CMU_FSYS */
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#define CLK_MOUT_FSYS_BUS_USER 1
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#define CLK_MOUT_FSYS_MMC_CARD_USER 2
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#define CLK_MOUT_FSYS_MMC_EMBD_USER 3
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#define CLK_MOUT_FSYS_MMC_SDIO_USER 4
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#define CLK_MOUT_FSYS_USB30DRD_USER 4
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#define CLK_GOUT_MMC_CARD_ACLK 5
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#define CLK_GOUT_MMC_CARD_SDCLKIN 6
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#define CLK_GOUT_MMC_EMBD_ACLK 7
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#define CLK_GOUT_MMC_EMBD_SDCLKIN 8
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#define CLK_GOUT_MMC_SDIO_ACLK 9
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#define CLK_GOUT_MMC_SDIO_SDCLKIN 10
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#define FSYS_NR_CLK 11
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#endif /* _DT_BINDINGS_CLOCK_EXYNOS_7885_H */
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