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Documentation wrongly tells that book3s/32 CPU have hash MMU. 603 and e300 core only have software loaded TLB. 755, 7450 family and e600 core have both hash MMU and software loaded TLB. This can be selected by setting a bit in HID2 (755) or HID0 (others). At the time being this is not supported by the kernel. Make this explicit in the documentation. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/261923c075d1cb49d02493685e8585d4ea2a5197.1593698951.git.christophe.leroy@csgroup.eu
225 lines
6.2 KiB
ReStructuredText
225 lines
6.2 KiB
ReStructuredText
============
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CPU Families
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============
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This document tries to summarise some of the different cpu families that exist
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and are supported by arch/powerpc.
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Book3S (aka sPAPR)
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------------------
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- Hash MMU (except 603 and e300)
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- Software loaded TLB (603 and e300)
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- Selectable Software loaded TLB in addition to hash MMU (755, 7450, e600)
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- Mix of 32 & 64 bit::
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+--------------+ +----------------+
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| Old POWER | --------------> | RS64 (threads) |
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+--------------+ +----------------+
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v
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+--------------+ +----------------+ +------+
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| 601 | --------------> | 603 | ---> | e300 |
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+--------------+ +----------------+ +------+
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v v
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+--------------+ +-----+ +----------------+ +-------+
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| 604 | | 755 | <--- | 750 (G3) | ---> | 750CX |
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+--------------+ +-----+ +----------------+ +-------+
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v v v
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+--------------+ +----------------+ +-------+
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| 620 (64 bit) | | 7400 | | 750CL |
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+--------------+ +----------------+ +-------+
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v v v
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+--------------+ +----------------+ +-------+
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| POWER3/630 | | 7410 | | 750FX |
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+--------------+ +----------------+ +-------+
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v v
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+--------------+ +----------------+
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| POWER3+ | | 7450 |
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+--------------+ +----------------+
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v v
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+--------------+ +----------------+
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| POWER4 | | 7455 |
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+--------------+ +----------------+
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v v
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+--------------+ +-------+ +----------------+
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| POWER4+ | --> | 970 | | 7447 |
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+--------------+ +-------+ +----------------+
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v v v
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+--------------+ +-------+ +----------------+
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| POWER5 | | 970FX | | 7448 |
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+--------------+ +-------+ +----------------+
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v v v
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+--------------+ +-------+ +----------------+
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| POWER5+ | | 970MP | | e600 |
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+--------------+ +-------+ +----------------+
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v
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+--------------+
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| POWER5++ |
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+--------------+
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v
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+--------------+ +-------+
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| POWER6 | <-?-> | Cell |
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+--------------+ +-------+
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v
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+--------------+
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| POWER7 |
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+--------------+
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v
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+--------------+
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| POWER7+ |
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+--------------+
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v
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+--------------+
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| POWER8 |
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+--------------+
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+---------------+
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| PA6T (64 bit) |
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+---------------+
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IBM BookE
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---------
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- Software loaded TLB.
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- All 32 bit::
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+--------------+
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| 401 |
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+--------------+
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v
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+--------------+
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| 403 |
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+--------------+
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v
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+--------------+
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| 405 |
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+--------------+
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v
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+--------------+
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| 440 |
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+--------------+
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v
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+--------------+ +----------------+
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| 450 | --> | BG/P |
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+--------------+ +----------------+
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v
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+--------------+
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| 460 |
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+--------------+
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v
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+--------------+
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| 476 |
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+--------------+
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Motorola/Freescale 8xx
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----------------------
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- Software loaded with hardware assist.
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- All 32 bit::
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+-------------+
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| MPC8xx Core |
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+-------------+
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Freescale BookE
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---------------
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- Software loaded TLB.
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- e6500 adds HW loaded indirect TLB entries.
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- Mix of 32 & 64 bit::
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+--------------+
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| e200 |
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+--------------+
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+--------------------------------+
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| e500 |
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+--------------------------------+
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v
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+--------------------------------+
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| e500v2 |
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+--------------------------------+
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v
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+--------------------------------+
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| e500mc (Book3e) |
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+--------------------------------+
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v
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+--------------------------------+
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| e5500 (64 bit) |
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+--------------------------------+
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v
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+--------------------------------+
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| e6500 (HW TLB) (Multithreaded) |
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+--------------------------------+
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IBM A2 core
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-----------
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- Book3E, software loaded TLB + HW loaded indirect TLB entries.
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- 64 bit::
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+--------------+ +----------------+
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| A2 core | --> | WSP |
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+--------------+ +----------------+
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v
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+--------------+
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| BG/Q |
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+--------------+
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