mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-11-30 23:54:04 +08:00
216a094de2
Rationale:
Reduces attack surface on kernel devs opening the links for MITM
as HTTPS traffic is much harder to manipulate.
Deterministic algorithm:
For each file:
If not .svg:
For each line:
If doesn't contain `\bxmlns\b`:
For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`:
If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`:
If both the HTTP and HTTPS versions
return 200 OK and serve the same content:
Replace HTTP with HTTPS.
Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
320 lines
7.4 KiB
C
320 lines
7.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* ECAP PWM driver
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*
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* Copyright (C) 2012 Texas Instruments, Inc. - https://www.ti.com/
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/pm_runtime.h>
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#include <linux/pwm.h>
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#include <linux/of_device.h>
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/* ECAP registers and bits definitions */
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#define CAP1 0x08
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#define CAP2 0x0C
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#define CAP3 0x10
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#define CAP4 0x14
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#define ECCTL2 0x2A
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#define ECCTL2_APWM_POL_LOW BIT(10)
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#define ECCTL2_APWM_MODE BIT(9)
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#define ECCTL2_SYNC_SEL_DISA (BIT(7) | BIT(6))
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#define ECCTL2_TSCTR_FREERUN BIT(4)
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struct ecap_context {
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u32 cap3;
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u32 cap4;
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u16 ecctl2;
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};
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struct ecap_pwm_chip {
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struct pwm_chip chip;
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unsigned int clk_rate;
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void __iomem *mmio_base;
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struct ecap_context ctx;
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};
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static inline struct ecap_pwm_chip *to_ecap_pwm_chip(struct pwm_chip *chip)
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{
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return container_of(chip, struct ecap_pwm_chip, chip);
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}
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/*
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* period_ns = 10^9 * period_cycles / PWM_CLK_RATE
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* duty_ns = 10^9 * duty_cycles / PWM_CLK_RATE
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*/
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static int ecap_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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int duty_ns, int period_ns)
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{
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struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
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u32 period_cycles, duty_cycles;
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unsigned long long c;
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u16 value;
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if (period_ns > NSEC_PER_SEC)
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return -ERANGE;
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c = pc->clk_rate;
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c = c * period_ns;
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do_div(c, NSEC_PER_SEC);
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period_cycles = (u32)c;
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if (period_cycles < 1) {
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period_cycles = 1;
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duty_cycles = 1;
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} else {
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c = pc->clk_rate;
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c = c * duty_ns;
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do_div(c, NSEC_PER_SEC);
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duty_cycles = (u32)c;
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}
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pm_runtime_get_sync(pc->chip.dev);
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value = readw(pc->mmio_base + ECCTL2);
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/* Configure APWM mode & disable sync option */
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value |= ECCTL2_APWM_MODE | ECCTL2_SYNC_SEL_DISA;
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writew(value, pc->mmio_base + ECCTL2);
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if (!pwm_is_enabled(pwm)) {
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/* Update active registers if not running */
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writel(duty_cycles, pc->mmio_base + CAP2);
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writel(period_cycles, pc->mmio_base + CAP1);
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} else {
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/*
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* Update shadow registers to configure period and
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* compare values. This helps current PWM period to
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* complete on reconfiguring
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*/
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writel(duty_cycles, pc->mmio_base + CAP4);
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writel(period_cycles, pc->mmio_base + CAP3);
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}
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if (!pwm_is_enabled(pwm)) {
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value = readw(pc->mmio_base + ECCTL2);
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/* Disable APWM mode to put APWM output Low */
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value &= ~ECCTL2_APWM_MODE;
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writew(value, pc->mmio_base + ECCTL2);
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}
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pm_runtime_put_sync(pc->chip.dev);
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return 0;
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}
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static int ecap_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
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enum pwm_polarity polarity)
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{
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struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
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u16 value;
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pm_runtime_get_sync(pc->chip.dev);
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value = readw(pc->mmio_base + ECCTL2);
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if (polarity == PWM_POLARITY_INVERSED)
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/* Duty cycle defines LOW period of PWM */
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value |= ECCTL2_APWM_POL_LOW;
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else
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/* Duty cycle defines HIGH period of PWM */
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value &= ~ECCTL2_APWM_POL_LOW;
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writew(value, pc->mmio_base + ECCTL2);
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pm_runtime_put_sync(pc->chip.dev);
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return 0;
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}
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static int ecap_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
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u16 value;
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/* Leave clock enabled on enabling PWM */
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pm_runtime_get_sync(pc->chip.dev);
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/*
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* Enable 'Free run Time stamp counter mode' to start counter
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* and 'APWM mode' to enable APWM output
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*/
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value = readw(pc->mmio_base + ECCTL2);
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value |= ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE;
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writew(value, pc->mmio_base + ECCTL2);
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return 0;
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}
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static void ecap_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
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u16 value;
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/*
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* Disable 'Free run Time stamp counter mode' to stop counter
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* and 'APWM mode' to put APWM output to low
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*/
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value = readw(pc->mmio_base + ECCTL2);
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value &= ~(ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE);
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writew(value, pc->mmio_base + ECCTL2);
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/* Disable clock on PWM disable */
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pm_runtime_put_sync(pc->chip.dev);
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}
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static void ecap_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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if (pwm_is_enabled(pwm)) {
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dev_warn(chip->dev, "Removing PWM device without disabling\n");
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pm_runtime_put_sync(chip->dev);
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}
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}
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static const struct pwm_ops ecap_pwm_ops = {
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.free = ecap_pwm_free,
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.config = ecap_pwm_config,
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.set_polarity = ecap_pwm_set_polarity,
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.enable = ecap_pwm_enable,
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.disable = ecap_pwm_disable,
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.owner = THIS_MODULE,
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};
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static const struct of_device_id ecap_of_match[] = {
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{ .compatible = "ti,am3352-ecap" },
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{ .compatible = "ti,am33xx-ecap" },
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{},
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};
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MODULE_DEVICE_TABLE(of, ecap_of_match);
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static int ecap_pwm_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct ecap_pwm_chip *pc;
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struct resource *r;
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struct clk *clk;
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int ret;
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pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
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if (!pc)
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return -ENOMEM;
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clk = devm_clk_get(&pdev->dev, "fck");
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if (IS_ERR(clk)) {
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if (of_device_is_compatible(np, "ti,am33xx-ecap")) {
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dev_warn(&pdev->dev, "Binding is obsolete.\n");
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clk = devm_clk_get(pdev->dev.parent, "fck");
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}
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}
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if (IS_ERR(clk)) {
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dev_err(&pdev->dev, "failed to get clock\n");
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return PTR_ERR(clk);
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}
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pc->clk_rate = clk_get_rate(clk);
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if (!pc->clk_rate) {
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dev_err(&pdev->dev, "failed to get clock rate\n");
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return -EINVAL;
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}
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pc->chip.dev = &pdev->dev;
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pc->chip.ops = &ecap_pwm_ops;
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pc->chip.of_xlate = of_pwm_xlate_with_flags;
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pc->chip.of_pwm_n_cells = 3;
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pc->chip.base = -1;
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pc->chip.npwm = 1;
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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pc->mmio_base = devm_ioremap_resource(&pdev->dev, r);
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if (IS_ERR(pc->mmio_base))
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return PTR_ERR(pc->mmio_base);
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ret = pwmchip_add(&pc->chip);
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if (ret < 0) {
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dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
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return ret;
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}
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platform_set_drvdata(pdev, pc);
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pm_runtime_enable(&pdev->dev);
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return 0;
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}
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static int ecap_pwm_remove(struct platform_device *pdev)
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{
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struct ecap_pwm_chip *pc = platform_get_drvdata(pdev);
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pm_runtime_disable(&pdev->dev);
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return pwmchip_remove(&pc->chip);
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}
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#ifdef CONFIG_PM_SLEEP
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static void ecap_pwm_save_context(struct ecap_pwm_chip *pc)
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{
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pm_runtime_get_sync(pc->chip.dev);
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pc->ctx.ecctl2 = readw(pc->mmio_base + ECCTL2);
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pc->ctx.cap4 = readl(pc->mmio_base + CAP4);
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pc->ctx.cap3 = readl(pc->mmio_base + CAP3);
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pm_runtime_put_sync(pc->chip.dev);
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}
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static void ecap_pwm_restore_context(struct ecap_pwm_chip *pc)
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{
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writel(pc->ctx.cap3, pc->mmio_base + CAP3);
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writel(pc->ctx.cap4, pc->mmio_base + CAP4);
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writew(pc->ctx.ecctl2, pc->mmio_base + ECCTL2);
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}
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static int ecap_pwm_suspend(struct device *dev)
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{
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struct ecap_pwm_chip *pc = dev_get_drvdata(dev);
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struct pwm_device *pwm = pc->chip.pwms;
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ecap_pwm_save_context(pc);
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/* Disable explicitly if PWM is running */
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if (pwm_is_enabled(pwm))
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pm_runtime_put_sync(dev);
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return 0;
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}
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static int ecap_pwm_resume(struct device *dev)
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{
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struct ecap_pwm_chip *pc = dev_get_drvdata(dev);
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struct pwm_device *pwm = pc->chip.pwms;
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/* Enable explicitly if PWM was running */
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if (pwm_is_enabled(pwm))
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pm_runtime_get_sync(dev);
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ecap_pwm_restore_context(pc);
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return 0;
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}
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#endif
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static SIMPLE_DEV_PM_OPS(ecap_pwm_pm_ops, ecap_pwm_suspend, ecap_pwm_resume);
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static struct platform_driver ecap_pwm_driver = {
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.driver = {
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.name = "ecap",
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.of_match_table = ecap_of_match,
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.pm = &ecap_pwm_pm_ops,
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},
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.probe = ecap_pwm_probe,
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.remove = ecap_pwm_remove,
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};
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module_platform_driver(ecap_pwm_driver);
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MODULE_DESCRIPTION("ECAP PWM driver");
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MODULE_AUTHOR("Texas Instruments");
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MODULE_LICENSE("GPL");
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