linux/drivers/cxl/core
Dan Williams 516b300c4c cxl/memdev: Formalize endpoint port linkage
Move the endpoint port that the cxl_mem driver establishes from drvdata
to a first class attribute. This is in preparation for device-memory
drivers reusing the CXL core for memory region management. Those drivers
need a type-safe method to retrieve their CXL port linkage. Leave
drvdata for private usage of the cxl_mem driver not external consumers
of a 'struct cxl_memdev' object.

Reviewed-by: Fan Ni <fan.ni@samsung.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/168679264292.3436160.3901392135863405807.stgit@dwillia2-xfh.jf.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2023-06-25 14:31:33 -07:00
..
core.h cxl/memdev: Trace inject and clear poison as cxl_poison events 2023-04-23 12:08:39 -07:00
hdm.c cxl/hdm: Default CXL_DEVTYPE_DEVMEM decoders to CXL_DECODER_DEVMEM 2023-06-25 14:31:08 -07:00
Makefile cxl/pci: Move tracepoint definitions to drivers/cxl/core/ 2023-01-04 17:11:11 -08:00
mbox.c cxl/memdev: Make mailbox functionality optional 2023-06-25 14:31:08 -07:00
memdev.c cxl/memdev: Formalize endpoint port linkage 2023-06-25 14:31:33 -07:00
pci.c cxl: Wait Memory_Info_Valid before access memory related info 2023-05-18 16:42:41 -07:00
pmem.c cxl/memdev: Formalize endpoint port linkage 2023-06-25 14:31:33 -07:00
port.c cxl/memdev: Formalize endpoint port linkage 2023-06-25 14:31:33 -07:00
region.c cxl/region: Manage decoder target_type at decoder-attach time 2023-06-25 14:31:09 -07:00
regs.c cxl/regs: Clarify when a 'struct cxl_register_map' is input vs output 2023-06-25 14:31:08 -07:00
suspend.c PM: CXL: Disable suspend 2022-04-22 16:09:42 -07:00
trace.c cxl/trace: Add an HPA to cxl_poison trace events 2023-04-23 11:46:13 -07:00
trace.h cxl/memdev: Trace inject and clear poison as cxl_poison events 2023-04-23 12:08:39 -07:00