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9a4435375c
These are the various new source code files for the Hisilicon RoCE driver for ARM architecture. Signed-off-by: Wei Hu <xavier.huwei@huawei.com> Signed-off-by: Nenglong Zhao <zhaonenglong@hisilicon.com> Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
81 lines
2.6 KiB
C
81 lines
2.6 KiB
C
/*
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* Copyright (c) 2016 Hisilicon Limited.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef _HNS_ROCE_CMD_H
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#define _HNS_ROCE_CMD_H
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#define HNS_ROCE_MAILBOX_SIZE 4096
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enum {
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/* TPT commands */
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HNS_ROCE_CMD_SW2HW_MPT = 0xd,
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HNS_ROCE_CMD_HW2SW_MPT = 0xf,
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/* CQ commands */
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HNS_ROCE_CMD_SW2HW_CQ = 0x16,
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HNS_ROCE_CMD_HW2SW_CQ = 0x17,
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/* QP/EE commands */
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HNS_ROCE_CMD_RST2INIT_QP = 0x19,
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HNS_ROCE_CMD_INIT2RTR_QP = 0x1a,
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HNS_ROCE_CMD_RTR2RTS_QP = 0x1b,
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HNS_ROCE_CMD_RTS2RTS_QP = 0x1c,
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HNS_ROCE_CMD_2ERR_QP = 0x1e,
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HNS_ROCE_CMD_RTS2SQD_QP = 0x1f,
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HNS_ROCE_CMD_SQD2SQD_QP = 0x38,
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HNS_ROCE_CMD_SQD2RTS_QP = 0x20,
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HNS_ROCE_CMD_2RST_QP = 0x21,
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HNS_ROCE_CMD_QUERY_QP = 0x22,
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};
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enum {
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HNS_ROCE_CMD_TIME_CLASS_A = 10000,
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HNS_ROCE_CMD_TIME_CLASS_B = 10000,
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HNS_ROCE_CMD_TIME_CLASS_C = 10000,
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};
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struct hns_roce_cmd_mailbox {
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void *buf;
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dma_addr_t dma;
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};
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int hns_roce_cmd_mbox(struct hns_roce_dev *hr_dev, u64 in_param, u64 out_param,
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unsigned long in_modifier, u8 op_modifier, u16 op,
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unsigned long timeout);
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struct hns_roce_cmd_mailbox
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*hns_roce_alloc_cmd_mailbox(struct hns_roce_dev *hr_dev);
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void hns_roce_free_cmd_mailbox(struct hns_roce_dev *hr_dev,
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struct hns_roce_cmd_mailbox *mailbox);
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#endif /* _HNS_ROCE_CMD_H */
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