mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-29 22:14:41 +08:00
f9f28cdf21
It's quite common on i.MX that one gate bit controls the gating of multiple clocks, i.e. this is a shared gate. The patch adds the function imx_clk_gate2_shared() for such case. The clocks controlled by the same gate bits should call this function with a pointer to a single share count variable, so that the gate bits will only be operated on the first enabling and the last disabling of these shared gate clocks. Thanks to Gerhard Sittig <gsi@denx.de> for this idea. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
123 lines
3.7 KiB
C
123 lines
3.7 KiB
C
#ifndef __MACH_IMX_CLK_H
|
|
#define __MACH_IMX_CLK_H
|
|
|
|
#include <linux/spinlock.h>
|
|
#include <linux/clk-provider.h>
|
|
|
|
extern spinlock_t imx_ccm_lock;
|
|
|
|
extern void imx_cscmr1_fixup(u32 *val);
|
|
|
|
struct clk *imx_clk_pllv1(const char *name, const char *parent,
|
|
void __iomem *base);
|
|
|
|
struct clk *imx_clk_pllv2(const char *name, const char *parent,
|
|
void __iomem *base);
|
|
|
|
enum imx_pllv3_type {
|
|
IMX_PLLV3_GENERIC,
|
|
IMX_PLLV3_SYS,
|
|
IMX_PLLV3_USB,
|
|
IMX_PLLV3_AV,
|
|
IMX_PLLV3_ENET,
|
|
};
|
|
|
|
struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
|
|
const char *parent_name, void __iomem *base, u32 div_mask);
|
|
|
|
struct clk *clk_register_gate2(struct device *dev, const char *name,
|
|
const char *parent_name, unsigned long flags,
|
|
void __iomem *reg, u8 bit_idx,
|
|
u8 clk_gate_flags, spinlock_t *lock,
|
|
unsigned int *share_count);
|
|
|
|
struct clk * imx_obtain_fixed_clock(
|
|
const char *name, unsigned long rate);
|
|
|
|
static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
|
|
void __iomem *reg, u8 shift)
|
|
{
|
|
return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
|
|
shift, 0, &imx_ccm_lock, NULL);
|
|
}
|
|
|
|
static inline struct clk *imx_clk_gate2_shared(const char *name,
|
|
const char *parent, void __iomem *reg, u8 shift,
|
|
unsigned int *share_count)
|
|
{
|
|
return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
|
|
shift, 0, &imx_ccm_lock, share_count);
|
|
}
|
|
|
|
struct clk *imx_clk_pfd(const char *name, const char *parent_name,
|
|
void __iomem *reg, u8 idx);
|
|
|
|
struct clk *imx_clk_busy_divider(const char *name, const char *parent_name,
|
|
void __iomem *reg, u8 shift, u8 width,
|
|
void __iomem *busy_reg, u8 busy_shift);
|
|
|
|
struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
|
|
u8 width, void __iomem *busy_reg, u8 busy_shift,
|
|
const char **parent_names, int num_parents);
|
|
|
|
struct clk *imx_clk_fixup_divider(const char *name, const char *parent,
|
|
void __iomem *reg, u8 shift, u8 width,
|
|
void (*fixup)(u32 *val));
|
|
|
|
struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
|
|
u8 shift, u8 width, const char **parents,
|
|
int num_parents, void (*fixup)(u32 *val));
|
|
|
|
static inline struct clk *imx_clk_fixed(const char *name, int rate)
|
|
{
|
|
return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);
|
|
}
|
|
|
|
static inline struct clk *imx_clk_divider(const char *name, const char *parent,
|
|
void __iomem *reg, u8 shift, u8 width)
|
|
{
|
|
return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
|
|
reg, shift, width, 0, &imx_ccm_lock);
|
|
}
|
|
|
|
static inline struct clk *imx_clk_divider_flags(const char *name,
|
|
const char *parent, void __iomem *reg, u8 shift, u8 width,
|
|
unsigned long flags)
|
|
{
|
|
return clk_register_divider(NULL, name, parent, flags,
|
|
reg, shift, width, 0, &imx_ccm_lock);
|
|
}
|
|
|
|
static inline struct clk *imx_clk_gate(const char *name, const char *parent,
|
|
void __iomem *reg, u8 shift)
|
|
{
|
|
return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
|
|
shift, 0, &imx_ccm_lock);
|
|
}
|
|
|
|
static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
|
|
u8 shift, u8 width, const char **parents, int num_parents)
|
|
{
|
|
return clk_register_mux(NULL, name, parents, num_parents,
|
|
CLK_SET_RATE_NO_REPARENT, reg, shift,
|
|
width, 0, &imx_ccm_lock);
|
|
}
|
|
|
|
static inline struct clk *imx_clk_mux_flags(const char *name,
|
|
void __iomem *reg, u8 shift, u8 width, const char **parents,
|
|
int num_parents, unsigned long flags)
|
|
{
|
|
return clk_register_mux(NULL, name, parents, num_parents,
|
|
flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0,
|
|
&imx_ccm_lock);
|
|
}
|
|
|
|
static inline struct clk *imx_clk_fixed_factor(const char *name,
|
|
const char *parent, unsigned int mult, unsigned int div)
|
|
{
|
|
return clk_register_fixed_factor(NULL, name, parent,
|
|
CLK_SET_RATE_PARENT, mult, div);
|
|
}
|
|
|
|
#endif
|