Christoph Hellwig 4f9bbcefa1 riscv: add support for MMIO access to the timer registers ... When running in M-mode we can't use the SBI to set the timer, and don't have access to the time CSR as that usually is emulated by M-mode. Instead provide code that directly accesses the MMIO for the timer. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Anup Patel <anup@brainfault.org> Acked-by: Thomas Gleixner <tglx@linutronix.de> # for drivers/clocksource [paul.walmsley@sifive.com: updated to apply; fixed checkpatch issue; timex.h now includes asm/mmio.h to resolve header file problems] Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>		2019-11-13 14:10:40 -08:00
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boot	riscv: dts: HiFive Unleashed: add default chosen/stdout-path	2019-10-14 12:30:30 -07:00
configs	RISC-V: Enable VIRTIO drivers in RV64 and RV32 defconfig	2019-09-19 05:44:35 -07:00
include	riscv: add support for MMIO access to the timer registers	2019-11-13 14:10:40 -08:00
kernel	riscv: cleanup the default power off implementation	2019-11-13 13:22:52 -08:00
lib	riscv: abstract out CSR names for supervisor vs machine mode	2019-11-05 09:20:42 -08:00
mm	riscv: implement remote sfence.i using IPIs	2019-11-13 13:24:21 -08:00
net	bpf, riscv: Enable zext optimization for more RV64G ALU ops	2019-07-05 23:55:41 +02:00
Kbuild	riscv: add arch/riscv/Kbuild	2019-08-30 17:34:00 -07:00
Kconfig	riscv: don't allow selecting SBI based drivers for M-mode	2019-11-13 13:20:02 -08:00
Kconfig.debug	RISC-V: Remove EARLY_PRINTK support	2018-12-17 10:23:46 -08:00
Kconfig.socs	riscv: select SiFive platform drivers with SOC_SIFIVE	2019-07-01 13:20:01 -07:00
Makefile	Kbuild updates for v5.4	2019-09-20 08:36:47 -07:00