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51f1092283
Upstream LiteX now defaults to using 32-bit CSR subregisters
(see https://github.com/enjoy-digital/litex/commit/a2b71fde).
This patch expands on commit 22447a99c9 ("drivers/soc/litex: add
LiteX SoC Controller driver"), adding support for handling both 8-
and 32-bit LiteX CSR (MMIO) subregisters, as determined by the
LITEX_SUBREG_SIZE Kconfig option.
NOTE that while LITEX_SUBREG_SIZE could theoretically be a device
tree property, defining it as a compile-time constant allows for
much better optimization of the resulting code. This is further
supported by the low expected usefulness of deploying the same
kernel across LiteX SoCs built with different CSR-Bus data widths.
Finally, the litex_[read|write][8|16|32|64]() accessors are
redefined in terms of litex_[get|set]_reg(), which, after compiler
optimization, will result in code as efficient as hardcoded shifts,
but with the added benefit of automatically matching the appropriate
LITEX_SUBREG_SIZE.
NOTE that litex_[get|set]_reg() nominally operate on 64-bit data,
but that will also be optimized by the compiler in situations where
narrower data is used from a call site.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
Signed-off-by: Stafford Horne <shorne@gmail.com>
105 lines
2.8 KiB
C
105 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* LiteX SoC Controller Driver
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*
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* Copyright (C) 2020 Antmicro <www.antmicro.com>
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*
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*/
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#include <linux/litex.h>
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/printk.h>
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#include <linux/module.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#define SCRATCH_REG_OFF 0x04
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#define SCRATCH_REG_VALUE 0x12345678
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#define SCRATCH_TEST_VALUE 0xdeadbeef
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/*
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* Check LiteX CSR read/write access
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*
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* This function reads and writes a scratch register in order to verify if CSR
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* access works.
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*
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* In case any problems are detected, the driver should panic.
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*
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* Access to the LiteX CSR is, by design, done in CPU native endianness.
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* The driver should not dynamically configure access functions when
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* the endianness mismatch is detected. Such situation indicates problems in
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* the soft SoC design and should be solved at the LiteX generator level,
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* not in the software.
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*/
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static int litex_check_csr_access(void __iomem *reg_addr)
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{
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unsigned long reg;
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reg = litex_read32(reg_addr + SCRATCH_REG_OFF);
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if (reg != SCRATCH_REG_VALUE) {
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panic("Scratch register read error - the system is probably broken! Expected: 0x%x but got: 0x%lx",
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SCRATCH_REG_VALUE, reg);
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return -EINVAL;
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}
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litex_write32(reg_addr + SCRATCH_REG_OFF, SCRATCH_TEST_VALUE);
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reg = litex_read32(reg_addr + SCRATCH_REG_OFF);
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if (reg != SCRATCH_TEST_VALUE) {
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panic("Scratch register write error - the system is probably broken! Expected: 0x%x but got: 0x%lx",
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SCRATCH_TEST_VALUE, reg);
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return -EINVAL;
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}
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/* restore original value of the SCRATCH register */
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litex_write32(reg_addr + SCRATCH_REG_OFF, SCRATCH_REG_VALUE);
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pr_info("LiteX SoC Controller driver initialized: subreg:%d, align:%d",
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LITEX_SUBREG_SIZE, LITEX_SUBREG_ALIGN);
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return 0;
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}
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struct litex_soc_ctrl_device {
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void __iomem *base;
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};
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static const struct of_device_id litex_soc_ctrl_of_match[] = {
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{.compatible = "litex,soc-controller"},
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{},
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};
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MODULE_DEVICE_TABLE(of, litex_soc_ctrl_of_match);
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static int litex_soc_ctrl_probe(struct platform_device *pdev)
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{
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struct litex_soc_ctrl_device *soc_ctrl_dev;
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soc_ctrl_dev = devm_kzalloc(&pdev->dev, sizeof(*soc_ctrl_dev), GFP_KERNEL);
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if (!soc_ctrl_dev)
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return -ENOMEM;
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soc_ctrl_dev->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(soc_ctrl_dev->base))
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return PTR_ERR(soc_ctrl_dev->base);
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return litex_check_csr_access(soc_ctrl_dev->base);
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}
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static struct platform_driver litex_soc_ctrl_driver = {
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.driver = {
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.name = "litex-soc-controller",
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.of_match_table = of_match_ptr(litex_soc_ctrl_of_match)
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},
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.probe = litex_soc_ctrl_probe,
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};
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module_platform_driver(litex_soc_ctrl_driver);
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MODULE_DESCRIPTION("LiteX SoC Controller driver");
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MODULE_AUTHOR("Antmicro <www.antmicro.com>");
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MODULE_LICENSE("GPL v2");
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