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0953fb2637
Now that entry code handles IRQ entry (including setting the IRQ regs)
before calling irqchip code, irqchip code can safely call
generic_handle_domain_irq(), and there's no functional reason for it to
call handle_domain_irq().
Let's cement this split of responsibility and remove handle_domain_irq()
entirely, updating irqchip drivers to call generic_handle_domain_irq().
For consistency, handle_domain_nmi() is similarly removed and replaced
with a generic_handle_domain_nmi() function which also does not perform
any entry logic.
Previously handle_domain_{irq,nmi}() had a WARN_ON() which would fire
when they were called in an inappropriate context. So that we can
identify similar issues going forward, similar WARN_ON_ONCE() logic is
added to the generic_handle_*() functions, and comments are updated for
clarity and consistency.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
261 lines
7.3 KiB
C
261 lines
7.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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//
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// Author: Steve Chen <schen@mvista.com>
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// Copyright (C) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
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// Author: Bartosz Golaszewski <bgolaszewski@baylibre.com>
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// Copyright (C) 2019, Texas Instruments
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//
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// TI Common Platform Interrupt Controller (cp_intc) driver
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#include <linux/export.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/irq-davinci-cp-intc.h>
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#include <linux/irqdomain.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <asm/exception.h>
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#define DAVINCI_CP_INTC_CTRL 0x04
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#define DAVINCI_CP_INTC_HOST_CTRL 0x0c
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#define DAVINCI_CP_INTC_GLOBAL_ENABLE 0x10
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#define DAVINCI_CP_INTC_SYS_STAT_IDX_CLR 0x24
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#define DAVINCI_CP_INTC_SYS_ENABLE_IDX_SET 0x28
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#define DAVINCI_CP_INTC_SYS_ENABLE_IDX_CLR 0x2c
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#define DAVINCI_CP_INTC_HOST_ENABLE_IDX_SET 0x34
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#define DAVINCI_CP_INTC_HOST_ENABLE_IDX_CLR 0x38
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#define DAVINCI_CP_INTC_PRIO_IDX 0x80
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#define DAVINCI_CP_INTC_SYS_STAT_CLR(n) (0x0280 + (n << 2))
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#define DAVINCI_CP_INTC_SYS_ENABLE_CLR(n) (0x0380 + (n << 2))
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#define DAVINCI_CP_INTC_CHAN_MAP(n) (0x0400 + (n << 2))
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#define DAVINCI_CP_INTC_SYS_POLARITY(n) (0x0d00 + (n << 2))
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#define DAVINCI_CP_INTC_SYS_TYPE(n) (0x0d80 + (n << 2))
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#define DAVINCI_CP_INTC_HOST_ENABLE(n) (0x1500 + (n << 2))
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#define DAVINCI_CP_INTC_PRI_INDX_MASK GENMASK(9, 0)
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#define DAVINCI_CP_INTC_GPIR_NONE BIT(31)
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static void __iomem *davinci_cp_intc_base;
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static struct irq_domain *davinci_cp_intc_irq_domain;
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static inline unsigned int davinci_cp_intc_read(unsigned int offset)
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{
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return readl_relaxed(davinci_cp_intc_base + offset);
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}
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static inline void davinci_cp_intc_write(unsigned long value,
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unsigned int offset)
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{
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writel_relaxed(value, davinci_cp_intc_base + offset);
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}
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static void davinci_cp_intc_ack_irq(struct irq_data *d)
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{
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davinci_cp_intc_write(d->hwirq, DAVINCI_CP_INTC_SYS_STAT_IDX_CLR);
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}
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static void davinci_cp_intc_mask_irq(struct irq_data *d)
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{
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/* XXX don't know why we need to disable nIRQ here... */
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davinci_cp_intc_write(1, DAVINCI_CP_INTC_HOST_ENABLE_IDX_CLR);
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davinci_cp_intc_write(d->hwirq, DAVINCI_CP_INTC_SYS_ENABLE_IDX_CLR);
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davinci_cp_intc_write(1, DAVINCI_CP_INTC_HOST_ENABLE_IDX_SET);
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}
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static void davinci_cp_intc_unmask_irq(struct irq_data *d)
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{
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davinci_cp_intc_write(d->hwirq, DAVINCI_CP_INTC_SYS_ENABLE_IDX_SET);
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}
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static int davinci_cp_intc_set_irq_type(struct irq_data *d,
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unsigned int flow_type)
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{
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unsigned int reg, mask, polarity, type;
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reg = BIT_WORD(d->hwirq);
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mask = BIT_MASK(d->hwirq);
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polarity = davinci_cp_intc_read(DAVINCI_CP_INTC_SYS_POLARITY(reg));
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type = davinci_cp_intc_read(DAVINCI_CP_INTC_SYS_TYPE(reg));
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switch (flow_type) {
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case IRQ_TYPE_EDGE_RISING:
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polarity |= mask;
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type |= mask;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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polarity &= ~mask;
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type |= mask;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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polarity |= mask;
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type &= ~mask;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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polarity &= ~mask;
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type &= ~mask;
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break;
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default:
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return -EINVAL;
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}
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davinci_cp_intc_write(polarity, DAVINCI_CP_INTC_SYS_POLARITY(reg));
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davinci_cp_intc_write(type, DAVINCI_CP_INTC_SYS_TYPE(reg));
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return 0;
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}
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static struct irq_chip davinci_cp_intc_irq_chip = {
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.name = "cp_intc",
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.irq_ack = davinci_cp_intc_ack_irq,
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.irq_mask = davinci_cp_intc_mask_irq,
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.irq_unmask = davinci_cp_intc_unmask_irq,
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.irq_set_type = davinci_cp_intc_set_irq_type,
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.flags = IRQCHIP_SKIP_SET_WAKE,
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};
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static asmlinkage void __exception_irq_entry
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davinci_cp_intc_handle_irq(struct pt_regs *regs)
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{
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int gpir, irqnr, none;
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/*
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* The interrupt number is in first ten bits. The NONE field set to 1
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* indicates a spurious irq.
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*/
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gpir = davinci_cp_intc_read(DAVINCI_CP_INTC_PRIO_IDX);
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irqnr = gpir & DAVINCI_CP_INTC_PRI_INDX_MASK;
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none = gpir & DAVINCI_CP_INTC_GPIR_NONE;
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if (unlikely(none)) {
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pr_err_once("%s: spurious irq!\n", __func__);
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return;
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}
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generic_handle_domain_irq(davinci_cp_intc_irq_domain, irqnr);
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}
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static int davinci_cp_intc_host_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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pr_debug("cp_intc_host_map(%d, 0x%lx)\n", virq, hw);
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irq_set_chip(virq, &davinci_cp_intc_irq_chip);
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irq_set_probe(virq);
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irq_set_handler(virq, handle_edge_irq);
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return 0;
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}
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static const struct irq_domain_ops davinci_cp_intc_irq_domain_ops = {
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.map = davinci_cp_intc_host_map,
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.xlate = irq_domain_xlate_onetwocell,
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};
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static int __init
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davinci_cp_intc_do_init(const struct davinci_cp_intc_config *config,
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struct device_node *node)
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{
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unsigned int num_regs = BITS_TO_LONGS(config->num_irqs);
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int offset, irq_base;
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void __iomem *req;
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req = request_mem_region(config->reg.start,
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resource_size(&config->reg),
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"davinci-cp-intc");
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if (!req) {
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pr_err("%s: register range busy\n", __func__);
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return -EBUSY;
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}
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davinci_cp_intc_base = ioremap(config->reg.start,
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resource_size(&config->reg));
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if (!davinci_cp_intc_base) {
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pr_err("%s: unable to ioremap register range\n", __func__);
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return -EINVAL;
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}
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davinci_cp_intc_write(0, DAVINCI_CP_INTC_GLOBAL_ENABLE);
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/* Disable all host interrupts */
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davinci_cp_intc_write(0, DAVINCI_CP_INTC_HOST_ENABLE(0));
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/* Disable system interrupts */
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for (offset = 0; offset < num_regs; offset++)
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davinci_cp_intc_write(~0,
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DAVINCI_CP_INTC_SYS_ENABLE_CLR(offset));
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/* Set to normal mode, no nesting, no priority hold */
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davinci_cp_intc_write(0, DAVINCI_CP_INTC_CTRL);
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davinci_cp_intc_write(0, DAVINCI_CP_INTC_HOST_CTRL);
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/* Clear system interrupt status */
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for (offset = 0; offset < num_regs; offset++)
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davinci_cp_intc_write(~0,
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DAVINCI_CP_INTC_SYS_STAT_CLR(offset));
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/* Enable nIRQ (what about nFIQ?) */
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davinci_cp_intc_write(1, DAVINCI_CP_INTC_HOST_ENABLE_IDX_SET);
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/* Default all priorities to channel 7. */
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num_regs = (config->num_irqs + 3) >> 2; /* 4 channels per register */
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for (offset = 0; offset < num_regs; offset++)
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davinci_cp_intc_write(0x07070707,
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DAVINCI_CP_INTC_CHAN_MAP(offset));
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irq_base = irq_alloc_descs(-1, 0, config->num_irqs, 0);
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if (irq_base < 0) {
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pr_err("%s: unable to allocate interrupt descriptors: %d\n",
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__func__, irq_base);
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return irq_base;
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}
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davinci_cp_intc_irq_domain = irq_domain_add_legacy(
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node, config->num_irqs, irq_base, 0,
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&davinci_cp_intc_irq_domain_ops, NULL);
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if (!davinci_cp_intc_irq_domain) {
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pr_err("%s: unable to create an interrupt domain\n", __func__);
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return -EINVAL;
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}
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set_handle_irq(davinci_cp_intc_handle_irq);
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/* Enable global interrupt */
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davinci_cp_intc_write(1, DAVINCI_CP_INTC_GLOBAL_ENABLE);
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return 0;
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}
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int __init davinci_cp_intc_init(const struct davinci_cp_intc_config *config)
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{
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return davinci_cp_intc_do_init(config, NULL);
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}
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static int __init davinci_cp_intc_of_init(struct device_node *node,
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struct device_node *parent)
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{
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struct davinci_cp_intc_config config = { };
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int ret;
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ret = of_address_to_resource(node, 0, &config.reg);
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if (ret) {
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pr_err("%s: unable to get the register range from device-tree\n",
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__func__);
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return ret;
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}
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ret = of_property_read_u32(node, "ti,intc-size", &config.num_irqs);
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if (ret) {
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pr_err("%s: unable to read the 'ti,intc-size' property\n",
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__func__);
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return ret;
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}
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return davinci_cp_intc_do_init(&config, node);
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}
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IRQCHIP_DECLARE(cp_intc, "ti,cp-intc", davinci_cp_intc_of_init);
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