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56d428ae1c
* Support for handling misaligned accesses in S-mode. * Probing for misaligned access support is now properly cached and handled in parallel. * PTDUMP now reflects the SW reserved bits, as well as the PBMT and NAPOT extensions. * Performance improvements for TLB flushing. * Support for many new relocations in the module loader. * Various bug fixes and cleanups. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmVOUCcTHHBhbG1lckBk YWJiZWx0LmNvbQAKCRAuExnzX7sYicJ2D/9S+9dnHYHVGTeJfr9Zf2T4r+qHBPyx LXbTAbgHN6139MgcRLMRlcUaQ04RVxuBCWhxewJ6mQiHiYNlullgKmJO8oYMS4uZ 2yQGHKhzKEVluXxe+qT6VW+zsP0cY6pDQ+e59AqZgyWzvATxMU4VtFfCDdjFG03I k/8Y3MUKSHAKzIHUsGHiMW5J2YRiM/iVehv2gZfanreulWlK6lyiV4AZ4KChu8Sa gix9QkFJw+9+7RHnouHvczt4xTqLPJQcdecLJsbisEI4VaaPtTVzkvXx/kwbMwX0 qkQnZ7I60fPHrCb9ccuedjDMa1Z0lrfwRldBGz9f9QaW37Eppirn6LA5JiZ1cA47 wKTwba6gZJCTRXELFTJLcv+Cwdy003E0y3iL5UK2rkbLqcxfvLdq1WAJU2t05Lmh aRQN10BtM2DZG+SNPlLoBpXPDw0Q3KOc20zGtuhmk010+X4yOK7WXlu8zNGLLE0+ yHamiZqAbpIUIEzwDdGbb95jywR1sUhNTbScuhj4Rc79ZqLtPxty1PUhnfqFat1R i3ngQtCbeUUYFS2YV9tKkXjLf/xkQNRbt7kQBowuvFuvfksl9UwMdRAWcE/h0M9P 7uz7cBFhuG0v/XblB7bUhYLkKITvP+ltSMyxaGlfpGqCLAH2KIztdZ2PLWLRdKeU +9dtZSQR6oBLqQ== =NhdR -----END PGP SIGNATURE----- Merge tag 'riscv-for-linus-6.7-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull more RISC-V updates from Palmer Dabbelt: - Support for handling misaligned accesses in S-mode - Probing for misaligned access support is now properly cached and handled in parallel - PTDUMP now reflects the SW reserved bits, as well as the PBMT and NAPOT extensions - Performance improvements for TLB flushing - Support for many new relocations in the module loader - Various bug fixes and cleanups * tag 'riscv-for-linus-6.7-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (51 commits) riscv: Optimize bitops with Zbb extension riscv: Rearrange hwcap.h and cpufeature.h drivers: perf: Do not broadcast to other cpus when starting a counter drivers: perf: Check find_first_bit() return value of: property: Add fw_devlink support for msi-parent RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTs riscv: Fix set_memory_XX() and set_direct_map_XX() by splitting huge linear mappings riscv: Don't use PGD entries for the linear mapping RISC-V: Probe misaligned access speed in parallel RISC-V: Remove __init on unaligned_emulation_finish() RISC-V: Show accurate per-hart isa in /proc/cpuinfo RISC-V: Don't rely on positional structure initialization riscv: Add tests for riscv module loading riscv: Add remaining module relocations riscv: Avoid unaligned access when relocating modules riscv: split cache ops out of dma-noncoherent.c riscv: Improve flush_tlb_kernel_range() riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlb riscv: Improve flush_tlb_range() for hugetlb pages riscv: Improve tlb_flush() ... |
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.. | ||
compat_vdso | ||
pi | ||
probes | ||
tests | ||
vdso | ||
.gitignore | ||
acpi.c | ||
alternative.c | ||
asm-offsets.c | ||
cacheinfo.c | ||
cfi.c | ||
compat_signal.c | ||
compat_syscall_table.c | ||
copy-unaligned.h | ||
copy-unaligned.S | ||
cpu_ops_sbi.c | ||
cpu_ops_spinwait.c | ||
cpu_ops.c | ||
cpu-hotplug.c | ||
cpu.c | ||
cpufeature.c | ||
crash_core.c | ||
crash_dump.c | ||
crash_save_regs.S | ||
efi-header.S | ||
efi.c | ||
elf_kexec.c | ||
entry.S | ||
fpu.S | ||
ftrace.c | ||
head.h | ||
head.S | ||
hibernate-asm.S | ||
hibernate.c | ||
image-vars.h | ||
irq.c | ||
jump_label.c | ||
kexec_relocate.S | ||
kgdb.c | ||
machine_kexec_file.c | ||
machine_kexec.c | ||
Makefile | ||
mcount-dyn.S | ||
mcount.S | ||
module-sections.c | ||
module.c | ||
patch.c | ||
perf_callchain.c | ||
perf_regs.c | ||
process.c | ||
ptrace.c | ||
reset.c | ||
riscv_ksyms.c | ||
sbi-ipi.c | ||
sbi.c | ||
setup.c | ||
signal.c | ||
smp.c | ||
smpboot.c | ||
soc.c | ||
stacktrace.c | ||
suspend_entry.S | ||
suspend.c | ||
sys_riscv.c | ||
syscall_table.c | ||
time.c | ||
traps_misaligned.c | ||
traps.c | ||
vdso.c | ||
vector.c | ||
vmlinux-xip.lds.S | ||
vmlinux.lds.S |