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87648cc925
The indices in nic_data->stats need to match the EF10_STAT_whatever enum values. In efx_nic_update_stats, only mask; gaps are removed in efx_ef10_update_stats. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
511 lines
14 KiB
C
511 lines
14 KiB
C
/****************************************************************************
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* Driver for Solarflare network controllers and boards
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* Copyright 2005-2006 Fen Systems Ltd.
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* Copyright 2006-2013 Solarflare Communications Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation, incorporated herein by reference.
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*/
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <linux/module.h>
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#include <linux/seq_file.h>
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#include <linux/cpu_rmap.h>
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#include "net_driver.h"
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#include "bitfield.h"
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#include "efx.h"
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#include "nic.h"
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#include "farch_regs.h"
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#include "io.h"
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#include "workarounds.h"
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/**************************************************************************
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*
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* Generic buffer handling
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* These buffers are used for interrupt status, MAC stats, etc.
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*
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**************************************************************************/
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int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer,
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unsigned int len, gfp_t gfp_flags)
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{
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buffer->addr = dma_zalloc_coherent(&efx->pci_dev->dev, len,
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&buffer->dma_addr, gfp_flags);
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if (!buffer->addr)
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return -ENOMEM;
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buffer->len = len;
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return 0;
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}
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void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
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{
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if (buffer->addr) {
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dma_free_coherent(&efx->pci_dev->dev, buffer->len,
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buffer->addr, buffer->dma_addr);
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buffer->addr = NULL;
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}
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}
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/* Check whether an event is present in the eventq at the current
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* read pointer. Only useful for self-test.
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*/
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bool efx_nic_event_present(struct efx_channel *channel)
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{
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return efx_event_present(efx_event(channel, channel->eventq_read_ptr));
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}
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void efx_nic_event_test_start(struct efx_channel *channel)
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{
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channel->event_test_cpu = -1;
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smp_wmb();
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channel->efx->type->ev_test_generate(channel);
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}
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void efx_nic_irq_test_start(struct efx_nic *efx)
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{
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efx->last_irq_cpu = -1;
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smp_wmb();
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efx->type->irq_test_generate(efx);
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}
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/* Hook interrupt handler(s)
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* Try MSI and then legacy interrupts.
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*/
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int efx_nic_init_interrupt(struct efx_nic *efx)
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{
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struct efx_channel *channel;
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unsigned int n_irqs;
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int rc;
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if (!EFX_INT_MODE_USE_MSI(efx)) {
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rc = request_irq(efx->legacy_irq,
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efx->type->irq_handle_legacy, IRQF_SHARED,
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efx->name, efx);
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if (rc) {
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netif_err(efx, drv, efx->net_dev,
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"failed to hook legacy IRQ %d\n",
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efx->pci_dev->irq);
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goto fail1;
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}
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return 0;
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}
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#ifdef CONFIG_RFS_ACCEL
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if (efx->interrupt_mode == EFX_INT_MODE_MSIX) {
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efx->net_dev->rx_cpu_rmap =
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alloc_irq_cpu_rmap(efx->n_rx_channels);
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if (!efx->net_dev->rx_cpu_rmap) {
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rc = -ENOMEM;
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goto fail1;
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}
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}
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#endif
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/* Hook MSI or MSI-X interrupt */
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n_irqs = 0;
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efx_for_each_channel(channel, efx) {
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rc = request_irq(channel->irq, efx->type->irq_handle_msi,
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IRQF_PROBE_SHARED, /* Not shared */
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efx->msi_context[channel->channel].name,
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&efx->msi_context[channel->channel]);
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if (rc) {
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netif_err(efx, drv, efx->net_dev,
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"failed to hook IRQ %d\n", channel->irq);
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goto fail2;
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}
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++n_irqs;
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#ifdef CONFIG_RFS_ACCEL
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if (efx->interrupt_mode == EFX_INT_MODE_MSIX &&
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channel->channel < efx->n_rx_channels) {
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rc = irq_cpu_rmap_add(efx->net_dev->rx_cpu_rmap,
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channel->irq);
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if (rc)
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goto fail2;
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}
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#endif
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}
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return 0;
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fail2:
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#ifdef CONFIG_RFS_ACCEL
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free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap);
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efx->net_dev->rx_cpu_rmap = NULL;
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#endif
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efx_for_each_channel(channel, efx) {
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if (n_irqs-- == 0)
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break;
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free_irq(channel->irq, &efx->msi_context[channel->channel]);
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}
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fail1:
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return rc;
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}
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void efx_nic_fini_interrupt(struct efx_nic *efx)
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{
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struct efx_channel *channel;
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#ifdef CONFIG_RFS_ACCEL
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free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap);
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efx->net_dev->rx_cpu_rmap = NULL;
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#endif
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/* Disable MSI/MSI-X interrupts */
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efx_for_each_channel(channel, efx)
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free_irq(channel->irq, &efx->msi_context[channel->channel]);
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/* Disable legacy interrupt */
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if (efx->legacy_irq)
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free_irq(efx->legacy_irq, efx);
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}
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/* Register dump */
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#define REGISTER_REVISION_A 1
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#define REGISTER_REVISION_B 2
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#define REGISTER_REVISION_C 3
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#define REGISTER_REVISION_Z 3 /* latest revision */
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struct efx_nic_reg {
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u32 offset:24;
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u32 min_revision:2, max_revision:2;
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};
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#define REGISTER(name, min_rev, max_rev) { \
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FR_ ## min_rev ## max_rev ## _ ## name, \
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REGISTER_REVISION_ ## min_rev, REGISTER_REVISION_ ## max_rev \
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}
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#define REGISTER_AA(name) REGISTER(name, A, A)
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#define REGISTER_AB(name) REGISTER(name, A, B)
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#define REGISTER_AZ(name) REGISTER(name, A, Z)
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#define REGISTER_BB(name) REGISTER(name, B, B)
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#define REGISTER_BZ(name) REGISTER(name, B, Z)
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#define REGISTER_CZ(name) REGISTER(name, C, Z)
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static const struct efx_nic_reg efx_nic_regs[] = {
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REGISTER_AZ(ADR_REGION),
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REGISTER_AZ(INT_EN_KER),
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REGISTER_BZ(INT_EN_CHAR),
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REGISTER_AZ(INT_ADR_KER),
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REGISTER_BZ(INT_ADR_CHAR),
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/* INT_ACK_KER is WO */
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/* INT_ISR0 is RC */
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REGISTER_AZ(HW_INIT),
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REGISTER_CZ(USR_EV_CFG),
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REGISTER_AB(EE_SPI_HCMD),
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REGISTER_AB(EE_SPI_HADR),
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REGISTER_AB(EE_SPI_HDATA),
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REGISTER_AB(EE_BASE_PAGE),
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REGISTER_AB(EE_VPD_CFG0),
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/* EE_VPD_SW_CNTL and EE_VPD_SW_DATA are not used */
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/* PMBX_DBG_IADDR and PBMX_DBG_IDATA are indirect */
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/* PCIE_CORE_INDIRECT is indirect */
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REGISTER_AB(NIC_STAT),
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REGISTER_AB(GPIO_CTL),
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REGISTER_AB(GLB_CTL),
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/* FATAL_INTR_KER and FATAL_INTR_CHAR are partly RC */
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REGISTER_BZ(DP_CTRL),
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REGISTER_AZ(MEM_STAT),
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REGISTER_AZ(CS_DEBUG),
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REGISTER_AZ(ALTERA_BUILD),
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REGISTER_AZ(CSR_SPARE),
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REGISTER_AB(PCIE_SD_CTL0123),
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REGISTER_AB(PCIE_SD_CTL45),
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REGISTER_AB(PCIE_PCS_CTL_STAT),
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/* DEBUG_DATA_OUT is not used */
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/* DRV_EV is WO */
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REGISTER_AZ(EVQ_CTL),
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REGISTER_AZ(EVQ_CNT1),
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REGISTER_AZ(EVQ_CNT2),
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REGISTER_AZ(BUF_TBL_CFG),
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REGISTER_AZ(SRM_RX_DC_CFG),
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REGISTER_AZ(SRM_TX_DC_CFG),
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REGISTER_AZ(SRM_CFG),
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/* BUF_TBL_UPD is WO */
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REGISTER_AZ(SRM_UPD_EVQ),
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REGISTER_AZ(SRAM_PARITY),
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REGISTER_AZ(RX_CFG),
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REGISTER_BZ(RX_FILTER_CTL),
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/* RX_FLUSH_DESCQ is WO */
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REGISTER_AZ(RX_DC_CFG),
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REGISTER_AZ(RX_DC_PF_WM),
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REGISTER_BZ(RX_RSS_TKEY),
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/* RX_NODESC_DROP is RC */
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REGISTER_AA(RX_SELF_RST),
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/* RX_DEBUG, RX_PUSH_DROP are not used */
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REGISTER_CZ(RX_RSS_IPV6_REG1),
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REGISTER_CZ(RX_RSS_IPV6_REG2),
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REGISTER_CZ(RX_RSS_IPV6_REG3),
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/* TX_FLUSH_DESCQ is WO */
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REGISTER_AZ(TX_DC_CFG),
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REGISTER_AA(TX_CHKSM_CFG),
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REGISTER_AZ(TX_CFG),
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/* TX_PUSH_DROP is not used */
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REGISTER_AZ(TX_RESERVED),
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REGISTER_BZ(TX_PACE),
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/* TX_PACE_DROP_QID is RC */
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REGISTER_BB(TX_VLAN),
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REGISTER_BZ(TX_IPFIL_PORTEN),
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REGISTER_AB(MD_TXD),
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REGISTER_AB(MD_RXD),
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REGISTER_AB(MD_CS),
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REGISTER_AB(MD_PHY_ADR),
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REGISTER_AB(MD_ID),
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/* MD_STAT is RC */
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REGISTER_AB(MAC_STAT_DMA),
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REGISTER_AB(MAC_CTRL),
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REGISTER_BB(GEN_MODE),
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REGISTER_AB(MAC_MC_HASH_REG0),
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REGISTER_AB(MAC_MC_HASH_REG1),
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REGISTER_AB(GM_CFG1),
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REGISTER_AB(GM_CFG2),
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/* GM_IPG and GM_HD are not used */
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REGISTER_AB(GM_MAX_FLEN),
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/* GM_TEST is not used */
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REGISTER_AB(GM_ADR1),
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REGISTER_AB(GM_ADR2),
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REGISTER_AB(GMF_CFG0),
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REGISTER_AB(GMF_CFG1),
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REGISTER_AB(GMF_CFG2),
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REGISTER_AB(GMF_CFG3),
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REGISTER_AB(GMF_CFG4),
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REGISTER_AB(GMF_CFG5),
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REGISTER_BB(TX_SRC_MAC_CTL),
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REGISTER_AB(XM_ADR_LO),
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REGISTER_AB(XM_ADR_HI),
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REGISTER_AB(XM_GLB_CFG),
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REGISTER_AB(XM_TX_CFG),
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REGISTER_AB(XM_RX_CFG),
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REGISTER_AB(XM_MGT_INT_MASK),
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REGISTER_AB(XM_FC),
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REGISTER_AB(XM_PAUSE_TIME),
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REGISTER_AB(XM_TX_PARAM),
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REGISTER_AB(XM_RX_PARAM),
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/* XM_MGT_INT_MSK (note no 'A') is RC */
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REGISTER_AB(XX_PWR_RST),
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REGISTER_AB(XX_SD_CTL),
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REGISTER_AB(XX_TXDRV_CTL),
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/* XX_PRBS_CTL, XX_PRBS_CHK and XX_PRBS_ERR are not used */
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/* XX_CORE_STAT is partly RC */
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};
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struct efx_nic_reg_table {
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u32 offset:24;
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u32 min_revision:2, max_revision:2;
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u32 step:6, rows:21;
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};
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#define REGISTER_TABLE_DIMENSIONS(_, offset, min_rev, max_rev, step, rows) { \
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offset, \
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REGISTER_REVISION_ ## min_rev, REGISTER_REVISION_ ## max_rev, \
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step, rows \
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}
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#define REGISTER_TABLE(name, min_rev, max_rev) \
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REGISTER_TABLE_DIMENSIONS( \
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name, FR_ ## min_rev ## max_rev ## _ ## name, \
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min_rev, max_rev, \
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FR_ ## min_rev ## max_rev ## _ ## name ## _STEP, \
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FR_ ## min_rev ## max_rev ## _ ## name ## _ROWS)
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#define REGISTER_TABLE_AA(name) REGISTER_TABLE(name, A, A)
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#define REGISTER_TABLE_AZ(name) REGISTER_TABLE(name, A, Z)
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#define REGISTER_TABLE_BB(name) REGISTER_TABLE(name, B, B)
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#define REGISTER_TABLE_BZ(name) REGISTER_TABLE(name, B, Z)
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#define REGISTER_TABLE_BB_CZ(name) \
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REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, B, B, \
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FR_BZ_ ## name ## _STEP, \
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FR_BB_ ## name ## _ROWS), \
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REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, C, Z, \
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FR_BZ_ ## name ## _STEP, \
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FR_CZ_ ## name ## _ROWS)
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#define REGISTER_TABLE_CZ(name) REGISTER_TABLE(name, C, Z)
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static const struct efx_nic_reg_table efx_nic_reg_tables[] = {
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/* DRIVER is not used */
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/* EVQ_RPTR, TIMER_COMMAND, USR_EV and {RX,TX}_DESC_UPD are WO */
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REGISTER_TABLE_BB(TX_IPFIL_TBL),
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REGISTER_TABLE_BB(TX_SRC_MAC_TBL),
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REGISTER_TABLE_AA(RX_DESC_PTR_TBL_KER),
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REGISTER_TABLE_BB_CZ(RX_DESC_PTR_TBL),
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REGISTER_TABLE_AA(TX_DESC_PTR_TBL_KER),
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REGISTER_TABLE_BB_CZ(TX_DESC_PTR_TBL),
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REGISTER_TABLE_AA(EVQ_PTR_TBL_KER),
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REGISTER_TABLE_BB_CZ(EVQ_PTR_TBL),
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/* We can't reasonably read all of the buffer table (up to 8MB!).
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* However this driver will only use a few entries. Reading
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* 1K entries allows for some expansion of queue count and
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* size before we need to change the version. */
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REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL_KER, FR_AA_BUF_FULL_TBL_KER,
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A, A, 8, 1024),
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REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL, FR_BZ_BUF_FULL_TBL,
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B, Z, 8, 1024),
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REGISTER_TABLE_CZ(RX_MAC_FILTER_TBL0),
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REGISTER_TABLE_BB_CZ(TIMER_TBL),
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REGISTER_TABLE_BB_CZ(TX_PACE_TBL),
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REGISTER_TABLE_BZ(RX_INDIRECTION_TBL),
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/* TX_FILTER_TBL0 is huge and not used by this driver */
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REGISTER_TABLE_CZ(TX_MAC_FILTER_TBL0),
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REGISTER_TABLE_CZ(MC_TREG_SMEM),
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/* MSIX_PBA_TABLE is not mapped */
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/* SRM_DBG is not mapped (and is redundant with BUF_FLL_TBL) */
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REGISTER_TABLE_BZ(RX_FILTER_TBL0),
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};
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size_t efx_nic_get_regs_len(struct efx_nic *efx)
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{
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const struct efx_nic_reg *reg;
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const struct efx_nic_reg_table *table;
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size_t len = 0;
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for (reg = efx_nic_regs;
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reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs);
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reg++)
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if (efx->type->revision >= reg->min_revision &&
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efx->type->revision <= reg->max_revision)
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len += sizeof(efx_oword_t);
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for (table = efx_nic_reg_tables;
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table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables);
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table++)
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if (efx->type->revision >= table->min_revision &&
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efx->type->revision <= table->max_revision)
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len += table->rows * min_t(size_t, table->step, 16);
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return len;
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}
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void efx_nic_get_regs(struct efx_nic *efx, void *buf)
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{
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const struct efx_nic_reg *reg;
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const struct efx_nic_reg_table *table;
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for (reg = efx_nic_regs;
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reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs);
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reg++) {
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if (efx->type->revision >= reg->min_revision &&
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efx->type->revision <= reg->max_revision) {
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efx_reado(efx, (efx_oword_t *)buf, reg->offset);
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buf += sizeof(efx_oword_t);
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}
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}
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for (table = efx_nic_reg_tables;
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table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables);
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table++) {
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size_t size, i;
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if (!(efx->type->revision >= table->min_revision &&
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efx->type->revision <= table->max_revision))
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continue;
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size = min_t(size_t, table->step, 16);
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for (i = 0; i < table->rows; i++) {
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switch (table->step) {
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case 4: /* 32-bit SRAM */
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efx_readd(efx, buf, table->offset + 4 * i);
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break;
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case 8: /* 64-bit SRAM */
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efx_sram_readq(efx,
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efx->membase + table->offset,
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buf, i);
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break;
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case 16: /* 128-bit-readable register */
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efx_reado_table(efx, buf, table->offset, i);
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break;
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case 32: /* 128-bit register, interleaved */
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efx_reado_table(efx, buf, table->offset, 2 * i);
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break;
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default:
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WARN_ON(1);
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return;
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}
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buf += size;
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}
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}
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}
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/**
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* efx_nic_describe_stats - Describe supported statistics for ethtool
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* @desc: Array of &struct efx_hw_stat_desc describing the statistics
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* @count: Length of the @desc array
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* @mask: Bitmask of which elements of @desc are enabled
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* @names: Buffer to copy names to, or %NULL. The names are copied
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* starting at intervals of %ETH_GSTRING_LEN bytes.
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*
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* Returns the number of visible statistics, i.e. the number of set
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* bits in the first @count bits of @mask for which a name is defined.
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*/
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size_t efx_nic_describe_stats(const struct efx_hw_stat_desc *desc, size_t count,
|
|
const unsigned long *mask, u8 *names)
|
|
{
|
|
size_t visible = 0;
|
|
size_t index;
|
|
|
|
for_each_set_bit(index, mask, count) {
|
|
if (desc[index].name) {
|
|
if (names) {
|
|
strlcpy(names, desc[index].name,
|
|
ETH_GSTRING_LEN);
|
|
names += ETH_GSTRING_LEN;
|
|
}
|
|
++visible;
|
|
}
|
|
}
|
|
|
|
return visible;
|
|
}
|
|
|
|
/**
|
|
* efx_nic_update_stats - Convert statistics DMA buffer to array of u64
|
|
* @desc: Array of &struct efx_hw_stat_desc describing the DMA buffer
|
|
* layout. DMA widths of 0, 16, 32 and 64 are supported; where
|
|
* the width is specified as 0 the corresponding element of
|
|
* @stats is not updated.
|
|
* @count: Length of the @desc array
|
|
* @mask: Bitmask of which elements of @desc are enabled
|
|
* @stats: Buffer to update with the converted statistics. The length
|
|
* of this array must be at least @count.
|
|
* @dma_buf: DMA buffer containing hardware statistics
|
|
* @accumulate: If set, the converted values will be added rather than
|
|
* directly stored to the corresponding elements of @stats
|
|
*/
|
|
void efx_nic_update_stats(const struct efx_hw_stat_desc *desc, size_t count,
|
|
const unsigned long *mask,
|
|
u64 *stats, const void *dma_buf, bool accumulate)
|
|
{
|
|
size_t index;
|
|
|
|
for_each_set_bit(index, mask, count) {
|
|
if (desc[index].dma_width) {
|
|
const void *addr = dma_buf + desc[index].offset;
|
|
u64 val;
|
|
|
|
switch (desc[index].dma_width) {
|
|
case 16:
|
|
val = le16_to_cpup((__le16 *)addr);
|
|
break;
|
|
case 32:
|
|
val = le32_to_cpup((__le32 *)addr);
|
|
break;
|
|
case 64:
|
|
val = le64_to_cpup((__le64 *)addr);
|
|
break;
|
|
default:
|
|
WARN_ON(1);
|
|
val = 0;
|
|
break;
|
|
}
|
|
|
|
if (accumulate)
|
|
stats[index] += val;
|
|
else
|
|
stats[index] = val;
|
|
}
|
|
}
|
|
}
|