Lad Prabhakar 9bd405c48b cache: ax45mp_cache: Align end size to cache boundary in ax45mp_dma_cache_wback() ... Align the end size to cache boundary size in ax45mp_dma_cache_wback() callback likewise done in ax45mp_dma_cache_inv() callback. Additionally return early in case of start == end. Fixes: d34599bcd2 ("cache: Add L2 cache management for Andes AX45MP RISC-V core") Reported-by: Pavel Machek <pavel@denx.de> Link: https://lore.kernel.org/cip-dev/ZYsdKDiw7G+kxQ3m@duo.ucw.cz/ Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>		2024-02-21 16:24:10 +00:00
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ax45mp_cache.c	cache: ax45mp_cache: Align end size to cache boundary in ax45mp_dma_cache_wback()	2024-02-21 16:24:10 +00:00
Kconfig	soc: sifive: shunt ccache driver to drivers/cache	2023-11-22 11:49:25 +00:00
Makefile	soc: sifive: shunt ccache driver to drivers/cache	2023-11-22 11:49:25 +00:00
sifive_ccache.c	soc: sifive: ccache: Add StarFive JH7100 support	2023-11-22 11:58:14 +00:00