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4e34614636
The R_INTC in the A31 and newer sun8i/sun50i SoCs is more similar to the
original sun4i interrupt controller than the sun7i/sun9i NMI controller.
It is used for two distinct purposes:
- To control the trigger, latch, and mask for the NMI input pin
- To provide the interrupt input for the ARISC coprocessor
As this interrupt controller is not documented, information about it
comes from vendor-provided firmware blobs and from experimentation.
Differences from the sun4i interrupt controller appear to be:
- It only has one or two registers of each kind (max 32 or 64 IRQs)
- Multiplexing logic is added to support additional inputs
- There is no FIQ-related logic
- There is no interrupt priority logic
In order to fulfill its two purposes, this hardware block combines four
types of IRQs. First, the NMI pin is routed to the "IRQ 0" input on this
chip, with a trigger type controlled by the NMI_CTRL_REG. The "IRQ 0
pending" output from this chip, if enabled, is then routed to a SPI IRQ
input on the GIC. In other words, bit 0 of IRQ_ENABLE_REG *does* affect
the NMI IRQ seen at the GIC.
The NMI is followed by a contiguous block of 15 "direct" (my name for
them) IRQ inputs that are connected in parallel to both R_INTC and the
GIC. Or in other words, these bits of IRQ_ENABLE_REG *do not* affect the
IRQs seen at the GIC.
Following the direct IRQs are the ARISC's copy of banked IRQs for shared
peripherals. These are not relevant to Linux. The remaining IRQs are
connected to a multiplexer and provide access to the first (up to) 128
SPIs from the ARISC. This range of SPIs overlaps with the direct IRQs.
Because of the 1:1 correspondence between R_INTC and GIC inputs, this is
a perfect scenario for using a stacked irqchip driver. We want to hook
into setting the NMI trigger type, but not actually handle any IRQ here.
To allow access to all multiplexed IRQs, this driver requires a new
binding where the interrupt number matches the GIC interrupt number.
(This moves the NMI from number 0 to 32 or 96, depending on the SoC.)
For simplicity, copy the three-cell GIC binding; this disambiguates
interrupt 0 in the old binding (the NMI) from interrupt 0 in the new
binding (SPI 0) by the number of cells.
Since R_INTC is in the always-on power domain, and its output is visible
to the power management coprocessor, a stacked irqchip driver provides a
simple way to add wakeup support to any of its IRQs. That is the next
patch; for now, just the NMI is moved over.
This commit mostly reverts commit 173bda53b3 ("irqchip/sunxi-nmi:
Support sun6i-a31-r-intc compatible").
Acked-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210118055040.21910-4-samuel@sholland.org
334 lines
7.8 KiB
Plaintext
334 lines
7.8 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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menu "Platform selection"
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config ARCH_ACTIONS
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bool "Actions Semi Platforms"
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select OWL_TIMER
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select PINCTRL
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help
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This enables support for the Actions Semiconductor S900 SoC family.
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config ARCH_AGILEX
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bool "Intel's Agilex SoCFPGA Family"
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help
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This enables support for Intel's Agilex SoCFPGA Family.
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config ARCH_SUNXI
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bool "Allwinner sunxi 64-bit SoC Family"
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select ARCH_HAS_RESET_CONTROLLER
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN_HIERARCHY
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select IRQ_FASTEOI_HIERARCHY_HANDLERS
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select PINCTRL
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select RESET_CONTROLLER
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help
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This enables support for Allwinner sunxi based SoCs like the A64.
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config ARCH_ALPINE
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bool "Annapurna Labs Alpine platform"
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select ALPINE_MSI if PCI
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help
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This enables support for the Annapurna Labs Alpine
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Soc family.
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config ARCH_BCM2835
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bool "Broadcom BCM2835 family"
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select TIMER_OF
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select GPIOLIB
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select MFD_CORE
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select PINCTRL
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select PINCTRL_BCM2835
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select ARM_AMBA
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select ARM_GIC
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select ARM_TIMER_SP804
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help
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This enables support for the Broadcom BCM2837 and BCM2711 SoC.
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These SoCs are used in the Raspberry Pi 3 and 4 devices.
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config ARCH_BCM4908
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bool "Broadcom BCM4908 family"
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select GPIOLIB
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help
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This enables support for the Broadcom BCM4906, BCM4908 and
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BCM49408 SoCs. These SoCs use Brahma-B53 cores and can be
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found in home routers.
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config ARCH_BCM_IPROC
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bool "Broadcom iProc SoC Family"
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select COMMON_CLK_IPROC
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select GPIOLIB
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select PINCTRL
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help
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This enables support for Broadcom iProc based SoCs
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config ARCH_BERLIN
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bool "Marvell Berlin SoC Family"
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select DW_APB_ICTL
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select DW_APB_TIMER_OF
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select GPIOLIB
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select PINCTRL
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help
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This enables support for Marvell Berlin SoC Family
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config ARCH_BITMAIN
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bool "Bitmain SoC Platforms"
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help
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This enables support for the Bitmain SoC Family.
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config ARCH_BRCMSTB
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bool "Broadcom Set-Top-Box SoCs"
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select ARCH_HAS_RESET_CONTROLLER
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select BCM7038_L1_IRQ
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select BRCMSTB_L2_IRQ
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select GENERIC_IRQ_CHIP
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select PINCTRL
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help
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This enables support for Broadcom's ARMv8 Set Top Box SoCs
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config ARCH_EXYNOS
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bool "ARMv8 based Samsung Exynos SoC family"
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select COMMON_CLK_SAMSUNG
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select EXYNOS_CHIPID
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select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS
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select EXYNOS_PMU
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select HAVE_S3C_RTC if RTC_CLASS
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select PINCTRL
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select PINCTRL_EXYNOS
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select PM_GENERIC_DOMAINS if PM
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select SOC_SAMSUNG
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help
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This enables support for ARMv8 based Samsung Exynos SoC family.
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config ARCH_SPARX5
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bool "ARMv8 based Microchip Sparx5 SoC family"
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select PINCTRL
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select DW_APB_TIMER_OF
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help
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This enables support for the Microchip Sparx5 ARMv8-based
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SoC family of TSN-capable gigabit switches.
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The SparX-5 Ethernet switch family provides a rich set of
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switching features such as advanced TCAM-based VLAN and QoS
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processing enabling delivery of differentiated services, and
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security through TCAM-based frame processing using versatile
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content aware processor (VCAP).
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config ARCH_K3
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bool "Texas Instruments Inc. K3 multicore SoC architecture"
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select PM_GENERIC_DOMAINS if PM
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select MAILBOX
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select SOC_TI
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select TI_MESSAGE_MANAGER
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select TI_SCI_PROTOCOL
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select TI_SCI_INTR_IRQCHIP
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select TI_SCI_INTA_IRQCHIP
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select TI_K3_SOCINFO
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help
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This enables support for Texas Instruments' K3 multicore SoC
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architecture.
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config ARCH_LAYERSCAPE
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bool "ARMv8 based Freescale Layerscape SoC family"
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select EDAC_SUPPORT
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help
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This enables support for the Freescale Layerscape SoC family.
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config ARCH_LG1K
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bool "LG Electronics LG1K SoC Family"
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help
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This enables support for LG Electronics LG1K SoC Family
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config ARCH_HISI
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bool "Hisilicon SoC Family"
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select ARM_TIMER_SP804
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select HISILICON_IRQ_MBIGEN if PCI
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select PINCTRL
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help
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This enables support for Hisilicon ARMv8 SoC family
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config ARCH_KEEMBAY
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bool "Keem Bay SoC"
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help
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This enables support for Intel Movidius SoC code-named Keem Bay.
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config ARCH_MEDIATEK
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bool "MediaTek SoC Family"
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select ARM_GIC
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select PINCTRL
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select MTK_TIMER
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help
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This enables support for MediaTek MT27xx, MT65xx, MT76xx
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& MT81xx ARMv8 SoCs
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config ARCH_MESON
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bool "Amlogic Platforms"
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select MESON_IRQ_GPIO
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help
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This enables support for the arm64 based Amlogic SoCs
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such as the s905, S905X/D, S912, A113X/D or S905X/D2
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config ARCH_MVEBU
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bool "Marvell EBU SoC Family"
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select ARMADA_AP806_SYSCON
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select ARMADA_CP110_SYSCON
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select ARMADA_37XX_CLK
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select GPIOLIB
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select GPIOLIB_IRQCHIP
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select MVEBU_GICP
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select MVEBU_ICU
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select MVEBU_ODMI
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select MVEBU_PIC
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select MVEBU_SEI
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select OF_GPIO
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select PINCTRL
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select PINCTRL_ARMADA_37XX
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select PINCTRL_ARMADA_AP806
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select PINCTRL_ARMADA_CP110
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help
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This enables support for Marvell EBU familly, including:
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- Armada 3700 SoC Family
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- Armada 7K SoC Family
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- Armada 8K SoC Family
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config ARCH_MXC
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bool "ARMv8 based NXP i.MX SoC family"
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select ARM64_ERRATUM_843419
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select ARM64_ERRATUM_845719 if COMPAT
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select IMX_GPCV2
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select IMX_GPCV2_PM_DOMAINS
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select PM
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select PM_GENERIC_DOMAINS
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select SOC_BUS
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select TIMER_IMX_SYS_CTR
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help
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This enables support for the ARMv8 based SoCs in the
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NXP i.MX family.
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config ARCH_QCOM
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bool "Qualcomm Platforms"
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select GPIOLIB
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select PINCTRL
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help
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This enables support for the ARMv8 based Qualcomm chipsets.
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config ARCH_REALTEK
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bool "Realtek Platforms"
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select RESET_CONTROLLER
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help
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This enables support for the ARMv8 based Realtek chipsets,
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like the RTD1295.
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config ARCH_RENESAS
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bool "Renesas SoC Platforms"
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select GPIOLIB
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select PINCTRL
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select SOC_BUS
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help
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This enables support for the ARMv8 based Renesas SoCs.
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config ARCH_ROCKCHIP
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bool "Rockchip Platforms"
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select ARCH_HAS_RESET_CONTROLLER
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select GPIOLIB
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select PINCTRL
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select PINCTRL_ROCKCHIP
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select PM
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select ROCKCHIP_TIMER
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help
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This enables support for the ARMv8 based Rockchip chipsets,
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like the RK3368.
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config ARCH_S32
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bool "NXP S32 SoC Family"
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help
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This enables support for the NXP S32 family of processors.
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config ARCH_SEATTLE
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bool "AMD Seattle SoC Family"
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help
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This enables support for AMD Seattle SOC Family
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config ARCH_STRATIX10
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bool "Altera's Stratix 10 SoCFPGA Family"
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help
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This enables support for Altera's Stratix 10 SoCFPGA Family.
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config ARCH_SYNQUACER
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bool "Socionext SynQuacer SoC Family"
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config ARCH_TEGRA
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bool "NVIDIA Tegra SoC Family"
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select ARCH_HAS_RESET_CONTROLLER
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select ARM_GIC_PM
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select CLKSRC_MMIO
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select TIMER_OF
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select GPIOLIB
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select PINCTRL
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select PM
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select PM_GENERIC_DOMAINS
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select RESET_CONTROLLER
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help
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This enables support for the NVIDIA Tegra SoC family.
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config ARCH_SPRD
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bool "Spreadtrum SoC platform"
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help
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Support for Spreadtrum ARM based SoCs
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config ARCH_THUNDER
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bool "Cavium Inc. Thunder SoC Family"
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help
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This enables support for Cavium's Thunder Family of SoCs.
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config ARCH_THUNDER2
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bool "Cavium ThunderX2 Server Processors"
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select GPIOLIB
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help
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This enables support for Cavium's ThunderX2 CN99XX family of
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server processors.
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config ARCH_UNIPHIER
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bool "Socionext UniPhier SoC Family"
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select ARCH_HAS_RESET_CONTROLLER
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select PINCTRL
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select RESET_CONTROLLER
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help
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This enables support for Socionext UniPhier SoC family.
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config ARCH_VEXPRESS
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bool "ARMv8 software model (Versatile Express)"
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select GPIOLIB
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select PM
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select PM_GENERIC_DOMAINS
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help
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This enables support for the ARMv8 software model (Versatile
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Express).
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config ARCH_VISCONTI
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bool "Toshiba Visconti SoC Family"
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select PINCTRL
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select PINCTRL_VISCONTI
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help
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This enables support for Toshiba Visconti SoCs Family.
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config ARCH_VULCAN
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def_bool n
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config ARCH_XGENE
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bool "AppliedMicro X-Gene SOC Family"
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help
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This enables support for AppliedMicro X-Gene SOC Family
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config ARCH_ZX
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bool "ZTE ZX SoC Family"
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select PINCTRL
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help
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This enables support for ZTE ZX SoC Family
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config ARCH_ZYNQMP
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bool "Xilinx ZynqMP Family"
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help
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This enables support for Xilinx ZynqMP Family
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endmenu
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