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4e11f5acb2
New Intel SoCs such as Broxton will have four PWMs per PCI (or ACPI) device. Each PWM has 1k of register space allocated from the parent device. Add support for this. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
34 lines
848 B
C
34 lines
848 B
C
/*
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* Intel Low Power Subsystem PWM controller driver
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*
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* Copyright (C) 2014, Intel Corporation
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*
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* Derived from the original pwm-lpss.c
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __PWM_LPSS_H
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#define __PWM_LPSS_H
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#include <linux/device.h>
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#include <linux/pwm.h>
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struct pwm_lpss_chip;
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struct pwm_lpss_boardinfo {
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unsigned long clk_rate;
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unsigned int npwm;
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};
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extern const struct pwm_lpss_boardinfo pwm_lpss_byt_info;
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extern const struct pwm_lpss_boardinfo pwm_lpss_bsw_info;
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struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r,
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const struct pwm_lpss_boardinfo *info);
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int pwm_lpss_remove(struct pwm_lpss_chip *lpwm);
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#endif /* __PWM_LPSS_H */
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