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48c4ac976a
This reverts commit d532f3d267.
The original commit has several problems:
1) Doesn't work with 64-bit kernels.
2) Calls TLBMISS_HANDLER_SETUP() before the code is generated.
3) Calls TLBMISS_HANDLER_SETUP() twice in per_cpu_trap_init() when
only one call is needed.
[ralf@linux-mips.org: Also revert the bits of the ASID patch which were
hidden in the KVM merge.]
Signed-off-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: "Steven J. Hill" <Steven.Hill@imgtec.com>
Cc: David Daney <david.daney@cavium.com>
Patchwork: https://patchwork.linux-mips.org/patch/5242/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
114 lines
2.7 KiB
C
114 lines
2.7 KiB
C
/*
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* Dump R4x00 TLB for debugging purposes.
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*
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* Copyright (C) 1994, 1995 by Waldorf Electronics, written by Ralf Baechle.
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* Copyright (C) 1999 by Silicon Graphics, Inc.
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*/
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <asm/mipsregs.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/tlbdebug.h>
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static inline const char *msk2str(unsigned int mask)
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{
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switch (mask) {
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case PM_4K: return "4kb";
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case PM_16K: return "16kb";
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case PM_64K: return "64kb";
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case PM_256K: return "256kb";
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#ifdef CONFIG_CPU_CAVIUM_OCTEON
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case PM_8K: return "8kb";
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case PM_32K: return "32kb";
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case PM_128K: return "128kb";
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case PM_512K: return "512kb";
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case PM_2M: return "2Mb";
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case PM_8M: return "8Mb";
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case PM_32M: return "32Mb";
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#endif
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#ifndef CONFIG_CPU_VR41XX
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case PM_1M: return "1Mb";
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case PM_4M: return "4Mb";
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case PM_16M: return "16Mb";
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case PM_64M: return "64Mb";
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case PM_256M: return "256Mb";
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case PM_1G: return "1Gb";
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#endif
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}
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return "";
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}
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#define BARRIER() \
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__asm__ __volatile__( \
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".set\tnoreorder\n\t" \
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"nop;nop;nop;nop;nop;nop;nop\n\t" \
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".set\treorder");
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static void dump_tlb(int first, int last)
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{
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unsigned long s_entryhi, entryhi, asid;
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unsigned long long entrylo0, entrylo1;
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unsigned int s_index, s_pagemask, pagemask, c0, c1, i;
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s_pagemask = read_c0_pagemask();
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s_entryhi = read_c0_entryhi();
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s_index = read_c0_index();
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asid = s_entryhi & 0xff;
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for (i = first; i <= last; i++) {
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write_c0_index(i);
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BARRIER();
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tlb_read();
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BARRIER();
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pagemask = read_c0_pagemask();
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entryhi = read_c0_entryhi();
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entrylo0 = read_c0_entrylo0();
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entrylo1 = read_c0_entrylo1();
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/* Unused entries have a virtual address of CKSEG0. */
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if ((entryhi & ~0x1ffffUL) != CKSEG0
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&& (entryhi & 0xff) == asid) {
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#ifdef CONFIG_32BIT
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int width = 8;
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#else
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int width = 11;
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#endif
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/*
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* Only print entries in use
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*/
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printk("Index: %2d pgmask=%s ", i, msk2str(pagemask));
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c0 = (entrylo0 >> 3) & 7;
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c1 = (entrylo1 >> 3) & 7;
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printk("va=%0*lx asid=%02lx\n",
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width, (entryhi & ~0x1fffUL),
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entryhi & 0xff);
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printk("\t[pa=%0*llx c=%d d=%d v=%d g=%d] ",
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width,
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(entrylo0 << 6) & PAGE_MASK, c0,
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(entrylo0 & 4) ? 1 : 0,
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(entrylo0 & 2) ? 1 : 0,
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(entrylo0 & 1) ? 1 : 0);
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printk("[pa=%0*llx c=%d d=%d v=%d g=%d]\n",
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width,
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(entrylo1 << 6) & PAGE_MASK, c1,
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(entrylo1 & 4) ? 1 : 0,
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(entrylo1 & 2) ? 1 : 0,
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(entrylo1 & 1) ? 1 : 0);
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}
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}
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printk("\n");
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write_c0_entryhi(s_entryhi);
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write_c0_index(s_index);
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write_c0_pagemask(s_pagemask);
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}
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void dump_tlb_all(void)
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{
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dump_tlb(0, current_cpu_data.tlbsize - 1);
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}
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