mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-19 00:54:41 +08:00
05d3b7c68e
The way hw_onecell_data is declared:
struct clk_hw_onecell_data {
unsigned int num;
struct clk_hw *hws[];
};
makes it impossible to have the clk_hw table declared outside while
using ARRAY_SIZE() to determine ".num" due to ".hws" being a flexible
array member.
Completely move out of hw_onecell_data and add a custom
devm_of_clk_add_hw_provider() "get" callback to retrieve the clk_hw
in order to finally get rid on the NR_CLKS define.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-6-38172d17c27a@linaro.org
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
148 lines
3.9 KiB
Plaintext
148 lines
3.9 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
|
|
menu "Clock support for Amlogic platforms"
|
|
depends on ARCH_MESON || COMPILE_TEST
|
|
|
|
config COMMON_CLK_MESON_REGMAP
|
|
tristate
|
|
select REGMAP
|
|
|
|
config COMMON_CLK_MESON_DUALDIV
|
|
tristate
|
|
select COMMON_CLK_MESON_REGMAP
|
|
|
|
config COMMON_CLK_MESON_MPLL
|
|
tristate
|
|
select COMMON_CLK_MESON_REGMAP
|
|
|
|
config COMMON_CLK_MESON_PHASE
|
|
tristate
|
|
select COMMON_CLK_MESON_REGMAP
|
|
|
|
config COMMON_CLK_MESON_PLL
|
|
tristate
|
|
select COMMON_CLK_MESON_REGMAP
|
|
|
|
config COMMON_CLK_MESON_SCLK_DIV
|
|
tristate
|
|
select COMMON_CLK_MESON_REGMAP
|
|
|
|
config COMMON_CLK_MESON_VID_PLL_DIV
|
|
tristate
|
|
select COMMON_CLK_MESON_REGMAP
|
|
|
|
config COMMON_CLK_MESON_CLKC_UTILS
|
|
tristate
|
|
|
|
config COMMON_CLK_MESON_AO_CLKC
|
|
tristate
|
|
select COMMON_CLK_MESON_REGMAP
|
|
select COMMON_CLK_MESON_CLKC_UTILS
|
|
select RESET_CONTROLLER
|
|
|
|
config COMMON_CLK_MESON_EE_CLKC
|
|
tristate
|
|
select COMMON_CLK_MESON_REGMAP
|
|
select COMMON_CLK_MESON_CLKC_UTILS
|
|
|
|
config COMMON_CLK_MESON_CPU_DYNDIV
|
|
tristate
|
|
select COMMON_CLK_MESON_REGMAP
|
|
|
|
config COMMON_CLK_MESON8B
|
|
bool "Meson8 SoC Clock controller support"
|
|
depends on ARM
|
|
default y
|
|
select COMMON_CLK_MESON_REGMAP
|
|
select COMMON_CLK_MESON_CLKC_UTILS
|
|
select COMMON_CLK_MESON_MPLL
|
|
select COMMON_CLK_MESON_PLL
|
|
select MFD_SYSCON
|
|
select RESET_CONTROLLER
|
|
help
|
|
Support for the clock controller on AmLogic S802 (Meson8),
|
|
S805 (Meson8b) and S812 (Meson8m2) devices. Say Y if you
|
|
want peripherals and CPU frequency scaling to work.
|
|
|
|
config COMMON_CLK_GXBB
|
|
tristate "GXBB and GXL SoC clock controllers support"
|
|
depends on ARM64
|
|
default y
|
|
select COMMON_CLK_MESON_REGMAP
|
|
select COMMON_CLK_MESON_DUALDIV
|
|
select COMMON_CLK_MESON_VID_PLL_DIV
|
|
select COMMON_CLK_MESON_MPLL
|
|
select COMMON_CLK_MESON_PLL
|
|
select COMMON_CLK_MESON_AO_CLKC
|
|
select COMMON_CLK_MESON_EE_CLKC
|
|
select MFD_SYSCON
|
|
help
|
|
Support for the clock controller on AmLogic S905 devices, aka gxbb.
|
|
Say Y if you want peripherals and CPU frequency scaling to work.
|
|
|
|
config COMMON_CLK_AXG
|
|
tristate "AXG SoC clock controllers support"
|
|
depends on ARM64
|
|
default y
|
|
select COMMON_CLK_MESON_REGMAP
|
|
select COMMON_CLK_MESON_DUALDIV
|
|
select COMMON_CLK_MESON_MPLL
|
|
select COMMON_CLK_MESON_PLL
|
|
select COMMON_CLK_MESON_AO_CLKC
|
|
select COMMON_CLK_MESON_EE_CLKC
|
|
select MFD_SYSCON
|
|
help
|
|
Support for the clock controller on AmLogic A113D devices, aka axg.
|
|
Say Y if you want peripherals and CPU frequency scaling to work.
|
|
|
|
config COMMON_CLK_AXG_AUDIO
|
|
tristate "Meson AXG Audio Clock Controller Driver"
|
|
depends on ARM64
|
|
select COMMON_CLK_MESON_REGMAP
|
|
select COMMON_CLK_MESON_PHASE
|
|
select COMMON_CLK_MESON_SCLK_DIV
|
|
select COMMON_CLK_MESON_CLKC_UTILS
|
|
select REGMAP_MMIO
|
|
help
|
|
Support for the audio clock controller on AmLogic A113D devices,
|
|
aka axg, Say Y if you want audio subsystem to work.
|
|
|
|
config COMMON_CLK_A1_PLL
|
|
tristate "Amlogic A1 SoC PLL controller support"
|
|
depends on ARM64
|
|
select COMMON_CLK_MESON_REGMAP
|
|
select COMMON_CLK_MESON_CLKC_UTILS
|
|
select COMMON_CLK_MESON_PLL
|
|
help
|
|
Support for the PLL clock controller on Amlogic A113L based
|
|
device, A1 SoC Family. Say Y if you want A1 PLL clock controller
|
|
to work.
|
|
|
|
config COMMON_CLK_A1_PERIPHERALS
|
|
tristate "Amlogic A1 SoC Peripherals clock controller support"
|
|
depends on ARM64
|
|
select COMMON_CLK_MESON_DUALDIV
|
|
select COMMON_CLK_MESON_REGMAP
|
|
select COMMON_CLK_MESON_CLKC_UTILS
|
|
help
|
|
Support for the Peripherals clock controller on Amlogic A113L based
|
|
device, A1 SoC Family. Say Y if you want A1 Peripherals clock
|
|
controller to work.
|
|
|
|
config COMMON_CLK_G12A
|
|
tristate "G12 and SM1 SoC clock controllers support"
|
|
depends on ARM64
|
|
default y
|
|
select COMMON_CLK_MESON_REGMAP
|
|
select COMMON_CLK_MESON_DUALDIV
|
|
select COMMON_CLK_MESON_MPLL
|
|
select COMMON_CLK_MESON_PLL
|
|
select COMMON_CLK_MESON_AO_CLKC
|
|
select COMMON_CLK_MESON_EE_CLKC
|
|
select COMMON_CLK_MESON_CPU_DYNDIV
|
|
select COMMON_CLK_MESON_VID_PLL_DIV
|
|
select MFD_SYSCON
|
|
help
|
|
Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2
|
|
devices, aka g12a. Say Y if you want peripherals to work.
|
|
endmenu
|