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c150b809f7
* Support for various vector-accelerated crypto routines. * Hibernation is now enabled for portable kernel builds. * mmap_rnd_bits_max is larger on systems with larger VAs. * Support for fast GUP. * Support for membarrier-based instruction cache synchronization. * Support for the Andes hart-level interrupt controller and PMU. * Some cleanups around unaligned access speed probing and Kconfig settings. * Support for ACPI LPI and CPPC. * Various cleanus related to barriers. * A handful of fixes. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmX9icgTHHBhbG1lckBk YWJiZWx0LmNvbQAKCRAuExnzX7sYib+UD/4xyL6UMixx6A06BVBL9UT4vOrxRvNr JIihG5y5QNMjes9DHWL35mZTMqFtQ0tq94ViWFLmJWloV/8KRVM2C9R9KX7vplf3 M/OwvP106spxgvNHoeQbycgs42RU1t2mpqT7N1iK2hCjqieP3vLn6hsSLXWTAG0L 3gQbQw6XCLC3hPyLq+nbFY2i4faeCmpXWmixoy/IvQ5calZQrRU0LNlP6lcMBhVo uocjG0uGAhrahw2s81jxcMZcxa3AvUCiplapdD5H5v9rBM85SkYJj2Q9SqdSorkb xzuimRnKPI5s47yM3pTfZY0qnQUYHV7PXXuw4WujpCQVQdhaG+Ggq63UUZA61J9t IzZK2zdcfHqICrGTtXImUzRT3dcc3oq+IFq4tTY+rEJm29hrXkAtx+qBm5xtMvax fJz5feJ/iT0u7MDj4Oq24n+Kpl+Olm+MJaZX3m5Ovi/9V6a9iK9HXqxg9/Fs0fMO +J/0kTgd8Vu9CYH7KNWz3uztcO9eMAH3VyzuXuab4BGj1i1Y/9EjpALQi7rDN73S OsYQX6NnzMkBV4dvElJVLXiPlvNlMHZZwdak5CqPb48jaJu6iiIZAuvOrG6/naGP wnQSLVA2WWWoOkl3AJhxfpa11CLhbMl9E2gYm1VtNvASXoSFIxlAq1Yv3sG8yjty 4ZT0rYFJOstYiQ== =3dL5 -----END PGP SIGNATURE----- Merge tag 'riscv-for-linus-6.9-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V updates from Palmer Dabbelt: - Support for various vector-accelerated crypto routines - Hibernation is now enabled for portable kernel builds - mmap_rnd_bits_max is larger on systems with larger VAs - Support for fast GUP - Support for membarrier-based instruction cache synchronization - Support for the Andes hart-level interrupt controller and PMU - Some cleanups around unaligned access speed probing and Kconfig settings - Support for ACPI LPI and CPPC - Various cleanus related to barriers - A handful of fixes * tag 'riscv-for-linus-6.9-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (66 commits) riscv: Fix syscall wrapper for >word-size arguments crypto: riscv - add vector crypto accelerated AES-CBC-CTS crypto: riscv - parallelize AES-CBC decryption riscv: Only flush the mm icache when setting an exec pte riscv: Use kcalloc() instead of kzalloc() riscv/barrier: Add missing space after ',' riscv/barrier: Consolidate fence definitions riscv/barrier: Define RISCV_FULL_BARRIER riscv/barrier: Define __{mb,rmb,wmb} RISC-V: defconfig: Enable CONFIG_ACPI_CPPC_CPUFREQ cpufreq: Move CPPC configs to common Kconfig and add RISC-V ACPI: RISC-V: Add CPPC driver ACPI: Enable ACPI_PROCESSOR for RISC-V ACPI: RISC-V: Add LPI driver cpuidle: RISC-V: Move few functions to arch/riscv riscv: Introduce set_compat_task() in asm/compat.h riscv: Introduce is_compat_thread() into compat.h riscv: add compile-time test into is_compat_task() riscv: Replace direct thread flag check with is_compat_task() riscv: Improve arch_get_mmap_end() macro ...
249 lines
5.3 KiB
C
249 lines
5.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* SMP initialisation and IPI support
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* Based on arch/arm64/kernel/smp.c
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*
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* Copyright (C) 2012 ARM Ltd.
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* Copyright (C) 2015 Regents of the University of California
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* Copyright (C) 2017 SiFive
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*/
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#include <linux/acpi.h>
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#include <linux/arch_topology.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <linux/kernel_stat.h>
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#include <linux/notifier.h>
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#include <linux/cpu.h>
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#include <linux/percpu.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/irq.h>
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#include <linux/of.h>
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#include <linux/sched/task_stack.h>
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#include <linux/sched/mm.h>
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#include <asm/cpufeature.h>
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#include <asm/cpu_ops.h>
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#include <asm/irq.h>
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#include <asm/mmu_context.h>
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#include <asm/numa.h>
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#include <asm/tlbflush.h>
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#include <asm/sections.h>
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#include <asm/smp.h>
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#include <uapi/asm/hwcap.h>
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#include <asm/vector.h>
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#include "head.h"
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static DECLARE_COMPLETION(cpu_running);
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void __init smp_prepare_cpus(unsigned int max_cpus)
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{
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int cpuid;
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unsigned int curr_cpuid;
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init_cpu_topology();
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curr_cpuid = smp_processor_id();
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store_cpu_topology(curr_cpuid);
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numa_store_cpu_info(curr_cpuid);
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numa_add_cpu(curr_cpuid);
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/* This covers non-smp usecase mandated by "nosmp" option */
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if (max_cpus == 0)
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return;
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for_each_possible_cpu(cpuid) {
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if (cpuid == curr_cpuid)
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continue;
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set_cpu_present(cpuid, true);
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numa_store_cpu_info(cpuid);
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}
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}
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#ifdef CONFIG_ACPI
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static unsigned int cpu_count = 1;
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static int __init acpi_parse_rintc(union acpi_subtable_headers *header, const unsigned long end)
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{
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unsigned long hart;
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static bool found_boot_cpu;
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struct acpi_madt_rintc *processor = (struct acpi_madt_rintc *)header;
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/*
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* Each RINTC structure in MADT will have a flag. If ACPI_MADT_ENABLED
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* bit in the flag is not enabled, it means OS should not try to enable
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* the cpu to which RINTC belongs.
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*/
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if (!(processor->flags & ACPI_MADT_ENABLED))
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return 0;
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if (BAD_MADT_ENTRY(processor, end))
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return -EINVAL;
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acpi_table_print_madt_entry(&header->common);
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hart = processor->hart_id;
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if (hart == INVALID_HARTID) {
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pr_warn("Invalid hartid\n");
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return 0;
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}
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if (hart == cpuid_to_hartid_map(0)) {
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BUG_ON(found_boot_cpu);
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found_boot_cpu = true;
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early_map_cpu_to_node(0, acpi_numa_get_nid(cpu_count));
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return 0;
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}
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if (cpu_count >= NR_CPUS) {
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pr_warn("NR_CPUS is too small for the number of ACPI tables.\n");
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return 0;
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}
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cpuid_to_hartid_map(cpu_count) = hart;
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early_map_cpu_to_node(cpu_count, acpi_numa_get_nid(cpu_count));
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cpu_count++;
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return 0;
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}
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static void __init acpi_parse_and_init_cpus(void)
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{
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acpi_table_parse_madt(ACPI_MADT_TYPE_RINTC, acpi_parse_rintc, 0);
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}
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#else
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#define acpi_parse_and_init_cpus(...) do { } while (0)
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#endif
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static void __init of_parse_and_init_cpus(void)
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{
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struct device_node *dn;
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unsigned long hart;
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bool found_boot_cpu = false;
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int cpuid = 1;
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int rc;
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for_each_of_cpu_node(dn) {
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rc = riscv_early_of_processor_hartid(dn, &hart);
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if (rc < 0)
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continue;
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if (hart == cpuid_to_hartid_map(0)) {
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BUG_ON(found_boot_cpu);
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found_boot_cpu = 1;
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early_map_cpu_to_node(0, of_node_to_nid(dn));
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continue;
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}
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if (cpuid >= NR_CPUS) {
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pr_warn("Invalid cpuid [%d] for hartid [%lu]\n",
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cpuid, hart);
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continue;
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}
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cpuid_to_hartid_map(cpuid) = hart;
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early_map_cpu_to_node(cpuid, of_node_to_nid(dn));
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cpuid++;
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}
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BUG_ON(!found_boot_cpu);
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if (cpuid > nr_cpu_ids)
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pr_warn("Total number of cpus [%d] is greater than nr_cpus option value [%d]\n",
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cpuid, nr_cpu_ids);
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}
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void __init setup_smp(void)
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{
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int cpuid;
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cpu_set_ops();
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if (acpi_disabled)
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of_parse_and_init_cpus();
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else
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acpi_parse_and_init_cpus();
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for (cpuid = 1; cpuid < nr_cpu_ids; cpuid++)
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if (cpuid_to_hartid_map(cpuid) != INVALID_HARTID)
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set_cpu_possible(cpuid, true);
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}
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static int start_secondary_cpu(int cpu, struct task_struct *tidle)
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{
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if (cpu_ops->cpu_start)
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return cpu_ops->cpu_start(cpu, tidle);
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return -EOPNOTSUPP;
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}
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int __cpu_up(unsigned int cpu, struct task_struct *tidle)
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{
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int ret = 0;
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tidle->thread_info.cpu = cpu;
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ret = start_secondary_cpu(cpu, tidle);
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if (!ret) {
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wait_for_completion_timeout(&cpu_running,
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msecs_to_jiffies(1000));
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if (!cpu_online(cpu)) {
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pr_crit("CPU%u: failed to come online\n", cpu);
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ret = -EIO;
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}
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} else {
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pr_crit("CPU%u: failed to start\n", cpu);
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}
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return ret;
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}
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void __init smp_cpus_done(unsigned int max_cpus)
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{
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}
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/*
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* C entry point for a secondary processor.
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*/
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asmlinkage __visible void smp_callin(void)
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{
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struct mm_struct *mm = &init_mm;
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unsigned int curr_cpuid = smp_processor_id();
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/* All kernel threads share the same mm context. */
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mmgrab(mm);
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current->active_mm = mm;
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store_cpu_topology(curr_cpuid);
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notify_cpu_starting(curr_cpuid);
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riscv_ipi_enable();
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numa_add_cpu(curr_cpuid);
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set_cpu_online(curr_cpuid, 1);
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if (has_vector()) {
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if (riscv_v_setup_vsize())
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elf_hwcap &= ~COMPAT_HWCAP_ISA_V;
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}
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riscv_user_isa_enable();
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/*
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* Remote TLB flushes are ignored while the CPU is offline, so emit
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* a local TLB flush right now just in case.
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*/
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local_flush_tlb_all();
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complete(&cpu_running);
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/*
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* Disable preemption before enabling interrupts, so we don't try to
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* schedule a CPU that hasn't actually started yet.
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*/
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local_irq_enable();
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cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
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}
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