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05b57273ac
Deprecate the legacy Rockchip PCIe PHY and encourage users to use per-lane PHY mode by setting #phy-cells to 1. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Acked-by: Rob Herring <robh@kernel.org>
37 lines
864 B
Plaintext
37 lines
864 B
Plaintext
Rockchip PCIE PHY
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-----------------------
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Required properties:
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- compatible: rockchip,rk3399-pcie-phy
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- clocks: Must contain an entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must be "refclk"
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- resets: Must contain an entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must be "phy"
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Required properties for legacy PHY mode (deprecated):
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- #phy-cells: must be 0
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Required properties for per-lane PHY mode (preferred):
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- #phy-cells: must be 1
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Example:
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grf: syscon@ff770000 {
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compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
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#address-cells = <1>;
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#size-cells = <1>;
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...
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pcie_phy: pcie-phy {
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compatible = "rockchip,rk3399-pcie-phy";
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#phy-cells = <0>;
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clocks = <&cru SCLK_PCIEPHY_REF>;
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clock-names = "refclk";
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resets = <&cru SRST_PCIEPHY>;
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reset-names = "phy";
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};
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};
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