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0fdebc5ec2
Based on the normalized pattern:
this file is licensed under the terms of the gnu general public
license version 2 this program is licensed as is without any warranty
of any kind whether express or implied
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference.
Reviewed-by: Allison Randal <allison@lohutok.net>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
149 lines
4.7 KiB
ArmAsm
149 lines
4.7 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* arch/arm/mach-lpc32xx/suspend.S
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*
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* Original authors: Dmitry Chigirev, Vitaly Wool <source@mvista.com>
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* Modified by Kevin Wells <kevin.wells@nxp.com>
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*
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* 2005 (c) MontaVista Software, Inc.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include "lpc32xx.h"
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/* Using named register defines makes the code easier to follow */
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#define WORK1_REG r0
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#define WORK2_REG r1
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#define SAVED_HCLK_DIV_REG r2
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#define SAVED_HCLK_PLL_REG r3
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#define SAVED_DRAM_CLKCTRL_REG r4
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#define SAVED_PWR_CTRL_REG r5
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#define CLKPWRBASE_REG r6
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#define EMCBASE_REG r7
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#define LPC32XX_EMC_STATUS_OFFS 0x04
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#define LPC32XX_EMC_STATUS_BUSY 0x1
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#define LPC32XX_EMC_STATUS_SELF_RFSH 0x4
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#define LPC32XX_CLKPWR_PWR_CTRL_OFFS 0x44
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#define LPC32XX_CLKPWR_HCLK_DIV_OFFS 0x40
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#define LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS 0x58
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#define CLKPWR_PCLK_DIV_MASK 0xFFFFFE7F
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.text
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ENTRY(lpc32xx_sys_suspend)
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@ Save a copy of the used registers in IRAM, r0 is corrupted
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adr r0, tmp_stack_end
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stmfd r0!, {r3 - r7, sp, lr}
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@ Load a few common register addresses
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adr WORK1_REG, reg_bases
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ldr CLKPWRBASE_REG, [WORK1_REG, #0]
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ldr EMCBASE_REG, [WORK1_REG, #4]
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ldr SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
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#LPC32XX_CLKPWR_PWR_CTRL_OFFS]
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orr WORK1_REG, SAVED_PWR_CTRL_REG, #LPC32XX_CLKPWR_SDRAM_SELF_RFSH
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@ Wait for SDRAM busy status to go busy and then idle
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@ This guarantees a small windows where DRAM isn't busy
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1:
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ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
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and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
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cmp WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
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bne 1b @ Branch while idle
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2:
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ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
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and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
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cmp WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
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beq 2b @ Branch until idle
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@ Setup self-refresh with support for manual exit of
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@ self-refresh mode
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str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
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orr WORK2_REG, WORK1_REG, #LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH
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str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
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str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
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@ Wait for self-refresh acknowledge, clocks to the DRAM device
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@ will automatically stop on start of self-refresh
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3:
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ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
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and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
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cmp WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
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bne 3b @ Branch until self-refresh mode starts
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@ Enter direct-run mode from run mode
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bic WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_SELECT_RUN_MODE
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str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
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@ Safe disable of DRAM clock in EMC block, prevents DDR sync
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@ issues on restart
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ldr SAVED_HCLK_DIV_REG, [CLKPWRBASE_REG,\
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#LPC32XX_CLKPWR_HCLK_DIV_OFFS]
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and WORK2_REG, SAVED_HCLK_DIV_REG, #CLKPWR_PCLK_DIV_MASK
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str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLK_DIV_OFFS]
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@ Save HCLK PLL state and disable HCLK PLL
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ldr SAVED_HCLK_PLL_REG, [CLKPWRBASE_REG,\
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#LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
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bic WORK2_REG, SAVED_HCLK_PLL_REG, #LPC32XX_CLKPWR_HCLKPLL_POWER_UP
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str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
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@ Enter stop mode until an enabled event occurs
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orr WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_STOP_MODE_CTRL
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str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
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.rept 9
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nop
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.endr
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@ Clear stop status
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bic WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_STOP_MODE_CTRL
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@ Restore original HCLK PLL value and wait for PLL lock
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str SAVED_HCLK_PLL_REG, [CLKPWRBASE_REG,\
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#LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
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4:
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ldr WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
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and WORK2_REG, WORK2_REG, #LPC32XX_CLKPWR_HCLKPLL_PLL_STS
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bne 4b
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@ Re-enter run mode with self-refresh flag cleared, but no DRAM
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@ update yet. DRAM is still in self-refresh
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str SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
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#LPC32XX_CLKPWR_PWR_CTRL_OFFS]
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@ Restore original DRAM clock mode to restore DRAM clocks
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str SAVED_HCLK_DIV_REG, [CLKPWRBASE_REG,\
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#LPC32XX_CLKPWR_HCLK_DIV_OFFS]
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@ Clear self-refresh mode
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orr WORK1_REG, SAVED_PWR_CTRL_REG,\
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#LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH
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str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
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str SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
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#LPC32XX_CLKPWR_PWR_CTRL_OFFS]
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@ Wait for EMC to clear self-refresh mode
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5:
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ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
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and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
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bne 5b @ Branch until self-refresh has exited
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@ restore regs and return
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adr r0, tmp_stack
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ldmfd r0!, {r3 - r7, sp, pc}
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reg_bases:
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.long IO_ADDRESS(LPC32XX_CLK_PM_BASE)
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.long IO_ADDRESS(LPC32XX_EMC_BASE)
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tmp_stack:
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.long 0, 0, 0, 0, 0, 0, 0
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tmp_stack_end:
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ENTRY(lpc32xx_sys_suspend_sz)
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.word . - lpc32xx_sys_suspend
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