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80606cb241
Most other drivers fill out the gpio_irq_chip using a struct gpio_irq_chip *girq helper variable for ease of reading. We also make a habit of explicitly assigning NULL and zero to the parent IRQs when using ordinary IRQ handlers in the driver, mostly for code readability and maintenance. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Cc: Dmitry Osipenko <digetx@gmail.com> Link: https://lore.kernel.org/r/20200716092835.69176-1-linus.walleij@linaro.org
370 lines
9.5 KiB
C
370 lines
9.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* MAXIM MAX77620 GPIO driver
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*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*/
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#include <linux/gpio/driver.h>
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#include <linux/interrupt.h>
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#include <linux/mfd/max77620.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#define GPIO_REG_ADDR(offset) (MAX77620_REG_GPIO0 + offset)
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struct max77620_gpio {
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struct gpio_chip gpio_chip;
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struct regmap *rmap;
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struct device *dev;
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struct mutex buslock; /* irq_bus_lock */
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unsigned int irq_type[MAX77620_GPIO_NR];
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bool irq_enabled[MAX77620_GPIO_NR];
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};
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static irqreturn_t max77620_gpio_irqhandler(int irq, void *data)
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{
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struct max77620_gpio *gpio = data;
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unsigned int value, offset;
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unsigned long pending;
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int err;
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err = regmap_read(gpio->rmap, MAX77620_REG_IRQ_LVL2_GPIO, &value);
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if (err < 0) {
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dev_err(gpio->dev, "REG_IRQ_LVL2_GPIO read failed: %d\n", err);
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return IRQ_NONE;
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}
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pending = value;
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for_each_set_bit(offset, &pending, MAX77620_GPIO_NR) {
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unsigned int virq;
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virq = irq_find_mapping(gpio->gpio_chip.irq.domain, offset);
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handle_nested_irq(virq);
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}
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return IRQ_HANDLED;
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}
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static void max77620_gpio_irq_mask(struct irq_data *data)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct max77620_gpio *gpio = gpiochip_get_data(chip);
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gpio->irq_enabled[data->hwirq] = false;
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}
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static void max77620_gpio_irq_unmask(struct irq_data *data)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct max77620_gpio *gpio = gpiochip_get_data(chip);
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gpio->irq_enabled[data->hwirq] = true;
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}
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static int max77620_gpio_set_irq_type(struct irq_data *data, unsigned int type)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct max77620_gpio *gpio = gpiochip_get_data(chip);
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unsigned int irq_type;
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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irq_type = MAX77620_CNFG_GPIO_INT_RISING;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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irq_type = MAX77620_CNFG_GPIO_INT_FALLING;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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irq_type = MAX77620_CNFG_GPIO_INT_RISING |
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MAX77620_CNFG_GPIO_INT_FALLING;
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break;
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default:
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return -EINVAL;
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}
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gpio->irq_type[data->hwirq] = irq_type;
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return 0;
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}
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static void max77620_gpio_bus_lock(struct irq_data *data)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct max77620_gpio *gpio = gpiochip_get_data(chip);
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mutex_lock(&gpio->buslock);
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}
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static void max77620_gpio_bus_sync_unlock(struct irq_data *data)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct max77620_gpio *gpio = gpiochip_get_data(chip);
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unsigned int value, offset = data->hwirq;
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int err;
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value = gpio->irq_enabled[offset] ? gpio->irq_type[offset] : 0;
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err = regmap_update_bits(gpio->rmap, GPIO_REG_ADDR(offset),
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MAX77620_CNFG_GPIO_INT_MASK, value);
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if (err < 0)
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dev_err(chip->parent, "failed to update interrupt mask: %d\n",
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err);
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mutex_unlock(&gpio->buslock);
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}
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static struct irq_chip max77620_gpio_irqchip = {
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.name = "max77620-gpio",
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.irq_mask = max77620_gpio_irq_mask,
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.irq_unmask = max77620_gpio_irq_unmask,
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.irq_set_type = max77620_gpio_set_irq_type,
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.irq_bus_lock = max77620_gpio_bus_lock,
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.irq_bus_sync_unlock = max77620_gpio_bus_sync_unlock,
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.flags = IRQCHIP_MASK_ON_SUSPEND,
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};
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static int max77620_gpio_dir_input(struct gpio_chip *gc, unsigned int offset)
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{
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struct max77620_gpio *mgpio = gpiochip_get_data(gc);
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int ret;
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ret = regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
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MAX77620_CNFG_GPIO_DIR_MASK,
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MAX77620_CNFG_GPIO_DIR_INPUT);
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if (ret < 0)
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dev_err(mgpio->dev, "CNFG_GPIOx dir update failed: %d\n", ret);
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return ret;
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}
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static int max77620_gpio_get(struct gpio_chip *gc, unsigned int offset)
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{
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struct max77620_gpio *mgpio = gpiochip_get_data(gc);
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unsigned int val;
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int ret;
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ret = regmap_read(mgpio->rmap, GPIO_REG_ADDR(offset), &val);
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if (ret < 0) {
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dev_err(mgpio->dev, "CNFG_GPIOx read failed: %d\n", ret);
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return ret;
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}
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if (val & MAX77620_CNFG_GPIO_DIR_MASK)
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return !!(val & MAX77620_CNFG_GPIO_INPUT_VAL_MASK);
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else
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return !!(val & MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK);
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}
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static int max77620_gpio_dir_output(struct gpio_chip *gc, unsigned int offset,
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int value)
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{
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struct max77620_gpio *mgpio = gpiochip_get_data(gc);
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u8 val;
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int ret;
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val = (value) ? MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH :
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MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW;
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ret = regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
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MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK, val);
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if (ret < 0) {
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dev_err(mgpio->dev, "CNFG_GPIOx val update failed: %d\n", ret);
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return ret;
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}
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ret = regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
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MAX77620_CNFG_GPIO_DIR_MASK,
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MAX77620_CNFG_GPIO_DIR_OUTPUT);
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if (ret < 0)
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dev_err(mgpio->dev, "CNFG_GPIOx dir update failed: %d\n", ret);
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return ret;
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}
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static int max77620_gpio_set_debounce(struct max77620_gpio *mgpio,
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unsigned int offset,
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unsigned int debounce)
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{
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u8 val;
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int ret;
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switch (debounce) {
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case 0:
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val = MAX77620_CNFG_GPIO_DBNC_None;
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break;
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case 1 ... 8000:
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val = MAX77620_CNFG_GPIO_DBNC_8ms;
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break;
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case 8001 ... 16000:
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val = MAX77620_CNFG_GPIO_DBNC_16ms;
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break;
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case 16001 ... 32000:
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val = MAX77620_CNFG_GPIO_DBNC_32ms;
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break;
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default:
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dev_err(mgpio->dev, "Illegal value %u\n", debounce);
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return -EINVAL;
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}
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ret = regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
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MAX77620_CNFG_GPIO_DBNC_MASK, val);
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if (ret < 0)
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dev_err(mgpio->dev, "CNFG_GPIOx_DBNC update failed: %d\n", ret);
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return ret;
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}
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static void max77620_gpio_set(struct gpio_chip *gc, unsigned int offset,
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int value)
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{
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struct max77620_gpio *mgpio = gpiochip_get_data(gc);
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u8 val;
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int ret;
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val = (value) ? MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH :
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MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW;
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ret = regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
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MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK, val);
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if (ret < 0)
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dev_err(mgpio->dev, "CNFG_GPIO_OUT update failed: %d\n", ret);
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}
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static int max77620_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
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unsigned long config)
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{
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struct max77620_gpio *mgpio = gpiochip_get_data(gc);
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switch (pinconf_to_config_param(config)) {
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case PIN_CONFIG_DRIVE_OPEN_DRAIN:
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return regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
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MAX77620_CNFG_GPIO_DRV_MASK,
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MAX77620_CNFG_GPIO_DRV_OPENDRAIN);
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case PIN_CONFIG_DRIVE_PUSH_PULL:
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return regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
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MAX77620_CNFG_GPIO_DRV_MASK,
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MAX77620_CNFG_GPIO_DRV_PUSHPULL);
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case PIN_CONFIG_INPUT_DEBOUNCE:
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return max77620_gpio_set_debounce(mgpio, offset,
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pinconf_to_config_argument(config));
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default:
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break;
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}
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return -ENOTSUPP;
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}
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static int max77620_gpio_irq_init_hw(struct gpio_chip *gc)
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{
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struct max77620_gpio *gpio = gpiochip_get_data(gc);
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unsigned int i;
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int err;
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/*
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* GPIO interrupts may be left ON after bootloader, hence let's
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* pre-initialize hardware to the expected state by disabling all
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* the interrupts.
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*/
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for (i = 0; i < MAX77620_GPIO_NR; i++) {
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err = regmap_update_bits(gpio->rmap, GPIO_REG_ADDR(i),
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MAX77620_CNFG_GPIO_INT_MASK, 0);
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if (err < 0) {
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dev_err(gpio->dev,
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"failed to disable interrupt: %d\n", err);
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return err;
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}
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}
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return 0;
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}
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static int max77620_gpio_probe(struct platform_device *pdev)
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{
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struct max77620_chip *chip = dev_get_drvdata(pdev->dev.parent);
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struct max77620_gpio *mgpio;
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struct gpio_irq_chip *girq;
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unsigned int gpio_irq;
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int ret;
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ret = platform_get_irq(pdev, 0);
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if (ret < 0)
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return ret;
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gpio_irq = ret;
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mgpio = devm_kzalloc(&pdev->dev, sizeof(*mgpio), GFP_KERNEL);
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if (!mgpio)
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return -ENOMEM;
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mutex_init(&mgpio->buslock);
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mgpio->rmap = chip->rmap;
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mgpio->dev = &pdev->dev;
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mgpio->gpio_chip.label = pdev->name;
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mgpio->gpio_chip.parent = pdev->dev.parent;
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mgpio->gpio_chip.direction_input = max77620_gpio_dir_input;
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mgpio->gpio_chip.get = max77620_gpio_get;
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mgpio->gpio_chip.direction_output = max77620_gpio_dir_output;
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mgpio->gpio_chip.set = max77620_gpio_set;
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mgpio->gpio_chip.set_config = max77620_gpio_set_config;
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mgpio->gpio_chip.ngpio = MAX77620_GPIO_NR;
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mgpio->gpio_chip.can_sleep = 1;
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mgpio->gpio_chip.base = -1;
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girq = &mgpio->gpio_chip.irq;
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girq->chip = &max77620_gpio_irqchip;
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/* This will let us handle the parent IRQ in the driver */
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girq->parent_handler = NULL;
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girq->num_parents = 0;
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girq->parents = NULL;
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girq->default_type = IRQ_TYPE_NONE;
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girq->handler = handle_edge_irq;
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girq->init_hw = max77620_gpio_irq_init_hw,
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girq->threaded = true;
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platform_set_drvdata(pdev, mgpio);
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ret = devm_gpiochip_add_data(&pdev->dev, &mgpio->gpio_chip, mgpio);
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if (ret < 0) {
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dev_err(&pdev->dev, "gpio_init: Failed to add max77620_gpio\n");
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return ret;
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}
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ret = devm_request_threaded_irq(&pdev->dev, gpio_irq, NULL,
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max77620_gpio_irqhandler, IRQF_ONESHOT,
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"max77620-gpio", mgpio);
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if (ret < 0) {
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dev_err(&pdev->dev, "failed to request IRQ: %d\n", ret);
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return ret;
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}
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return 0;
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}
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static const struct platform_device_id max77620_gpio_devtype[] = {
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{ .name = "max77620-gpio", },
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{ .name = "max20024-gpio", },
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{},
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};
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MODULE_DEVICE_TABLE(platform, max77620_gpio_devtype);
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static struct platform_driver max77620_gpio_driver = {
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.driver.name = "max77620-gpio",
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.probe = max77620_gpio_probe,
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.id_table = max77620_gpio_devtype,
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};
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module_platform_driver(max77620_gpio_driver);
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MODULE_DESCRIPTION("GPIO interface for MAX77620 and MAX20024 PMIC");
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MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
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MODULE_AUTHOR("Chaitanya Bandi <bandik@nvidia.com>");
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MODULE_ALIAS("platform:max77620-gpio");
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MODULE_LICENSE("GPL v2");
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