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This patch is added support Mediatek MT7925. 1. The firmware location of MT7925 will set to /lib/firmware/mediatek/mt7925 2. Add Mediatek private data in hdev to record the device for handle MT7925 flow. 3. Use the recoreded dev_id to condition chip reset flow. The information in /sys/kernel/debug/usb/devices about the MT7925U Bluetooth device is listed as the below T: Bus=01 Lev=01 Prnt=01 Port=00 Cnt=01 Dev#= 27 Spd=480 MxCh= 0 D: Ver= 2.10 Cls=ef(misc ) Sub=02 Prot=01 MxPS=64 #Cfgs= 1 P: Vendor=0e8d ProdID=7925 Rev= 1.00 S: Manufacturer=MediaTek Inc. S: Product=Wireless_Device S: SerialNumber=000000000 C:* #Ifs= 4 Cfg#= 1 Atr=e0 MxPwr=100mA A: FirstIf#= 0 IfCount= 3 Cls=e0(wlcon) Sub=01 Prot=01 I:* If#= 0 Alt= 0 #EPs= 5 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb E: Ad=81(I) Atr=03(Int.) MxPS= 16 Ivl=125us E: Ad=01(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=82(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=02(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=8f(I) Atr=03(Int.) MxPS= 2 Ivl=125us I:* If#= 1 Alt= 0 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb E: Ad=83(I) Atr=01(Isoc) MxPS= 0 Ivl=1ms E: Ad=03(O) Atr=01(Isoc) MxPS= 0 Ivl=1ms I: If#= 1 Alt= 1 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb E: Ad=83(I) Atr=01(Isoc) MxPS= 9 Ivl=1ms E: Ad=03(O) Atr=01(Isoc) MxPS= 9 Ivl=1ms I: If#= 1 Alt= 2 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb E: Ad=83(I) Atr=01(Isoc) MxPS= 17 Ivl=1ms E: Ad=03(O) Atr=01(Isoc) MxPS= 17 Ivl=1ms I: If#= 1 Alt= 3 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb E: Ad=83(I) Atr=01(Isoc) MxPS= 25 Ivl=1ms E: Ad=03(O) Atr=01(Isoc) MxPS= 25 Ivl=1ms I: If#= 1 Alt= 4 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb E: Ad=83(I) Atr=01(Isoc) MxPS= 33 Ivl=1ms E: Ad=03(O) Atr=01(Isoc) MxPS= 33 Ivl=1ms I: If#= 1 Alt= 5 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb E: Ad=83(I) Atr=01(Isoc) MxPS= 49 Ivl=1ms E: Ad=03(O) Atr=01(Isoc) MxPS= 49 Ivl=1ms I: If#= 1 Alt= 6 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb E: Ad=83(I) Atr=01(Isoc) MxPS= 63 Ivl=1ms E: Ad=03(O) Atr=01(Isoc) MxPS= 63 Ivl=1ms I:* If#= 2 Alt= 0 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=(none) E: Ad=8a(I) Atr=03(Int.) MxPS= 64 Ivl=125us E: Ad=0a(O) Atr=03(Int.) MxPS= 64 Ivl=125us I: If#= 2 Alt= 1 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=(none) E: Ad=8a(I) Atr=03(Int.) MxPS= 512 Ivl=125us E: Ad=0a(O) Atr=03(Int.) MxPS= 512 Ivl=125us I:* If#= 3 Alt= 0 #EPs= 9 Cls=ff(vend.) Sub=ff Prot=ff Driver=(none) E: Ad=84(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=85(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=08(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=04(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=05(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=06(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=07(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=09(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=86(I) Atr=03(Int.) MxPS= 2 Ivl=125us Signed-off-by: Peter Tsao <peter.tsao@mediatek.com> Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
160 lines
3.0 KiB
C
160 lines
3.0 KiB
C
/* SPDX-License-Identifier: ISC */
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/* Copyright (C) 2021 MediaTek Inc. */
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#define FIRMWARE_MT7622 "mediatek/mt7622pr2h.bin"
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#define FIRMWARE_MT7663 "mediatek/mt7663pr2h.bin"
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#define FIRMWARE_MT7668 "mediatek/mt7668pr2h.bin"
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#define FIRMWARE_MT7961 "mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin"
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#define FIRMWARE_MT7925 "mediatek/mt7925/BT_RAM_CODE_MT7925_1_1_hdr.bin"
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#define HCI_EV_WMT 0xe4
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#define HCI_WMT_MAX_EVENT_SIZE 64
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#define BTMTK_WMT_REG_WRITE 0x1
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#define BTMTK_WMT_REG_READ 0x2
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#define MT7921_BTSYS_RST 0x70002610
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#define MT7921_BTSYS_RST_WITH_GPIO BIT(7)
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#define MT7921_PINMUX_0 0x70005050
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#define MT7921_PINMUX_1 0x70005054
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#define MT7921_DLSTATUS 0x7c053c10
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#define BT_DL_STATE BIT(1)
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enum {
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BTMTK_WMT_PATCH_DWNLD = 0x1,
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BTMTK_WMT_TEST = 0x2,
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BTMTK_WMT_WAKEUP = 0x3,
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BTMTK_WMT_HIF = 0x4,
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BTMTK_WMT_FUNC_CTRL = 0x6,
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BTMTK_WMT_RST = 0x7,
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BTMTK_WMT_REGISTER = 0x8,
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BTMTK_WMT_SEMAPHORE = 0x17,
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};
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enum {
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BTMTK_WMT_INVALID,
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BTMTK_WMT_PATCH_UNDONE,
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BTMTK_WMT_PATCH_PROGRESS,
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BTMTK_WMT_PATCH_DONE,
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BTMTK_WMT_ON_UNDONE,
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BTMTK_WMT_ON_DONE,
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BTMTK_WMT_ON_PROGRESS,
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};
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struct btmtk_wmt_hdr {
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u8 dir;
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u8 op;
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__le16 dlen;
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u8 flag;
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} __packed;
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struct btmtk_hci_wmt_cmd {
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struct btmtk_wmt_hdr hdr;
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u8 data[];
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} __packed;
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struct btmtk_hci_wmt_evt {
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struct hci_event_hdr hhdr;
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struct btmtk_wmt_hdr whdr;
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} __packed;
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struct btmtk_hci_wmt_evt_funcc {
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struct btmtk_hci_wmt_evt hwhdr;
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__be16 status;
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} __packed;
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struct btmtk_hci_wmt_evt_reg {
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struct btmtk_hci_wmt_evt hwhdr;
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u8 rsv[2];
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u8 num;
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__le32 addr;
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__le32 val;
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} __packed;
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struct btmtk_tci_sleep {
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u8 mode;
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__le16 duration;
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__le16 host_duration;
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u8 host_wakeup_pin;
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u8 time_compensation;
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} __packed;
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struct btmtk_wakeon {
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u8 mode;
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u8 gpo;
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u8 active_high;
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__le16 enable_delay;
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__le16 wakeup_delay;
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} __packed;
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struct btmtk_sco {
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u8 clock_config;
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u8 transmit_format_config;
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u8 channel_format_config;
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u8 channel_select_config;
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} __packed;
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struct reg_read_cmd {
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u8 type;
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u8 rsv;
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u8 num;
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__le32 addr;
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} __packed;
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struct reg_write_cmd {
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u8 type;
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u8 rsv;
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u8 num;
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__le32 addr;
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__le32 data;
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__le32 mask;
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} __packed;
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struct btmtk_hci_wmt_params {
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u8 op;
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u8 flag;
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u16 dlen;
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const void *data;
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u32 *status;
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};
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struct btmediatek_data {
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u32 dev_id;
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};
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typedef int (*wmt_cmd_sync_func_t)(struct hci_dev *,
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struct btmtk_hci_wmt_params *);
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#if IS_ENABLED(CONFIG_BT_MTK)
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int btmtk_set_bdaddr(struct hci_dev *hdev, const bdaddr_t *bdaddr);
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int btmtk_setup_firmware_79xx(struct hci_dev *hdev, const char *fwname,
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wmt_cmd_sync_func_t wmt_cmd_sync);
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int btmtk_setup_firmware(struct hci_dev *hdev, const char *fwname,
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wmt_cmd_sync_func_t wmt_cmd_sync);
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#else
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static inline int btmtk_set_bdaddr(struct hci_dev *hdev,
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const bdaddr_t *bdaddr)
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{
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return -EOPNOTSUPP;
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}
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static int btmtk_setup_firmware_79xx(struct hci_dev *hdev, const char *fwname,
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wmt_cmd_sync_func_t wmt_cmd_sync)
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{
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return -EOPNOTSUPP;
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}
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static int btmtk_setup_firmware(struct hci_dev *hdev, const char *fwname,
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wmt_cmd_sync_func_t wmt_cmd_sync)
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{
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return -EOPNOTSUPP;
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}
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#endif
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