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Setup the cpu_logical_map during boot. Moreover, every SBI call and PLIC context are based on the physical hartid. Use the logical CPU to hartid mapping to pass correct hartid to respective functions. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
110 lines
3.2 KiB
C
110 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2012 Regents of the University of California
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* Copyright (C) 2017 SiFive
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*/
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/cpu.h>
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#include <linux/delay.h>
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#include <linux/irq.h>
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#include <asm/smp.h>
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#include <asm/sbi.h>
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/*
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* All RISC-V systems have a timer attached to every hart. These timers can be
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* read by the 'rdcycle' pseudo instruction, and can use the SBI to setup
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* events. In order to abstract the architecture-specific timer reading and
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* setting functions away from the clock event insertion code, we provide
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* function pointers to the clockevent subsystem that perform two basic
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* operations: rdtime() reads the timer on the current CPU, and
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* next_event(delta) sets the next timer event to 'delta' cycles in the future.
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* As the timers are inherently a per-cpu resource, these callbacks perform
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* operations on the current hart. There is guaranteed to be exactly one timer
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* per hart on all RISC-V systems.
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*/
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static int riscv_clock_next_event(unsigned long delta,
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struct clock_event_device *ce)
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{
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csr_set(sie, SIE_STIE);
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sbi_set_timer(get_cycles64() + delta);
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return 0;
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}
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static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) = {
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.name = "riscv_timer_clockevent",
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.features = CLOCK_EVT_FEAT_ONESHOT,
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.rating = 100,
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.set_next_event = riscv_clock_next_event,
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};
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/*
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* It is guaranteed that all the timers across all the harts are synchronized
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* within one tick of each other, so while this could technically go
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* backwards when hopping between CPUs, practically it won't happen.
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*/
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static unsigned long long riscv_clocksource_rdtime(struct clocksource *cs)
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{
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return get_cycles64();
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}
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static DEFINE_PER_CPU(struct clocksource, riscv_clocksource) = {
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.name = "riscv_clocksource",
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.rating = 300,
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.mask = CLOCKSOURCE_MASK(BITS_PER_LONG),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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.read = riscv_clocksource_rdtime,
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};
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static int riscv_timer_starting_cpu(unsigned int cpu)
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{
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struct clock_event_device *ce = per_cpu_ptr(&riscv_clock_event, cpu);
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ce->cpumask = cpumask_of(cpu);
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clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff);
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csr_set(sie, SIE_STIE);
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return 0;
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}
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static int riscv_timer_dying_cpu(unsigned int cpu)
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{
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csr_clear(sie, SIE_STIE);
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return 0;
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}
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/* called directly from the low-level interrupt handler */
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void riscv_timer_interrupt(void)
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{
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struct clock_event_device *evdev = this_cpu_ptr(&riscv_clock_event);
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csr_clear(sie, SIE_STIE);
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evdev->event_handler(evdev);
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}
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static int __init riscv_timer_init_dt(struct device_node *n)
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{
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int cpuid, hartid, error;
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struct clocksource *cs;
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hartid = riscv_of_processor_hartid(n);
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cpuid = riscv_hartid_to_cpuid(hartid);
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if (cpuid != smp_processor_id())
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return 0;
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cs = per_cpu_ptr(&riscv_clocksource, cpuid);
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clocksource_register_hz(cs, riscv_timebase);
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error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING,
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"clockevents/riscv/timer:starting",
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riscv_timer_starting_cpu, riscv_timer_dying_cpu);
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if (error)
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pr_err("RISCV timer register failed [%d] for cpu = [%d]\n",
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error, cpuid);
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return error;
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}
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TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt);
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