mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-15 15:04:27 +08:00
4bedea9454
The attached patches provides part 2 of an architecture implementation for the Tensilica Xtensa CPU series. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
67 lines
812 B
Plaintext
67 lines
812 B
Plaintext
OUTPUT_ARCH(xtensa)
|
|
|
|
SECTIONS
|
|
{
|
|
.start 0xD0200000 : { *(.start) }
|
|
|
|
.text :
|
|
{
|
|
__reloc_start = . ;
|
|
_text_start = . ;
|
|
*(.literal .text.literal .text)
|
|
_text_end = . ;
|
|
}
|
|
|
|
.rodata ALIGN(0x04):
|
|
{
|
|
*(.rodata)
|
|
*(.rodata1)
|
|
}
|
|
|
|
.data ALIGN(0x04):
|
|
{
|
|
*(.data)
|
|
*(.data1)
|
|
*(.sdata)
|
|
*(.sdata2)
|
|
*(.got.plt)
|
|
*(.got)
|
|
*(.dynamic)
|
|
}
|
|
|
|
__reloc_end = . ;
|
|
|
|
.initrd ALIGN(0x10) :
|
|
{
|
|
boot_initrd_start = . ;
|
|
*(.initrd)
|
|
boot_initrd_end = .;
|
|
}
|
|
|
|
. = ALIGN(0x10);
|
|
__image_load = . ;
|
|
.image 0xd0001000: AT(__image_load)
|
|
{
|
|
_image_start = .;
|
|
*(image)
|
|
. = (. + 3) & ~ 3;
|
|
_image_end = . ;
|
|
}
|
|
|
|
|
|
.bss ((LOADADDR(.image) + SIZEOF(.image) + 3) & ~ 3):
|
|
{
|
|
__bss_start = .;
|
|
*(.sbss)
|
|
*(.scommon)
|
|
*(.dynbss)
|
|
*(.bss)
|
|
__bss_end = .;
|
|
}
|
|
_end = .;
|
|
_param_start = .;
|
|
|
|
|
|
PROVIDE (end = .);
|
|
}
|