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4b73b6f7dc
Make the examples in Exynos Multi Core Timer bindings more readable and bring them closer to real DTS by using defines for interrupt flags. Fix also GIC interrupt type in example for Exynos4412 (from SPI to PPI). Suggested-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org>
125 lines
4.5 KiB
YAML
125 lines
4.5 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/timer/samsung,exynos4210-mct.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Samsung Exynos SoC Multi Core Timer (MCT)
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maintainers:
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- Krzysztof Kozlowski <krzk@kernel.org>
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description: |+
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The Samsung's Multi Core Timer (MCT) module includes two main blocks, the
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global timer and CPU local timers. The global timer is a 64-bit free running
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up-counter and can generate 4 interrupts when the counter reaches one of the
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four preset counter values. The CPU local timers are 32-bit free running
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down-counters and generate an interrupt when the counter expires. There is
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one CPU local timer instantiated in MCT for every CPU in the system.
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properties:
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compatible:
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enum:
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- samsung,exynos4210-mct
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- samsung,exynos4412-mct
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reg:
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maxItems: 1
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interrupts:
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description: |
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Interrupts should be put in specific order. This is, the local timer
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interrupts should be specified after the four global timer interrupts
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have been specified:
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0: Global Timer Interrupt 0
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1: Global Timer Interrupt 1
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2: Global Timer Interrupt 2
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3: Global Timer Interrupt 3
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4: Local Timer Interrupt 0
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5: Local Timer Interrupt 1
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6: ..
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7: ..
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i: Local Timer Interrupt n
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For MCT block that uses a per-processor interrupt for local timers, such
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as ones compatible with "samsung,exynos4412-mct", only one local timer
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interrupt might be specified, meaning that all local timers use the same
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per processor interrupt.
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minItems: 5 # 4 Global + 1 local
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maxItems: 20 # 4 Global + 16 local
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required:
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- compatible
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- interrupts
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- reg
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examples:
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- |
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// In this example, the IP contains two local timers, using separate
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// interrupts, so two local timer interrupts have been specified,
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// in addition to four global timer interrupts.
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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timer@10050000 {
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compatible = "samsung,exynos4210-mct";
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reg = <0x10050000 0x800>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
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};
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- |
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// In this example, the timer interrupts are connected to two separate
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// interrupt controllers. Hence, an interrupts-extended is needed.
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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timer@101c0000 {
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compatible = "samsung,exynos4210-mct";
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reg = <0x101C0000 0x800>;
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interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
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<&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
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<&combiner 12 6>,
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<&combiner 12 7>,
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<&gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<&gic GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
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};
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- |
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// In this example, the IP contains four local timers, but using
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// a per-processor interrupt to handle them. Only one first local
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// interrupt is specified.
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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timer@10050000 {
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compatible = "samsung,exynos4412-mct";
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reg = <0x10050000 0x800>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>;
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};
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- |
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// In this example, the IP contains four local timers, but using
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// a per-processor interrupt to handle them. All the local timer
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// interrupts are specified.
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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timer@10050000 {
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compatible = "samsung,exynos4412-mct";
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reg = <0x10050000 0x800>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>;
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};
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