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0953fb2637
Now that entry code handles IRQ entry (including setting the IRQ regs)
before calling irqchip code, irqchip code can safely call
generic_handle_domain_irq(), and there's no functional reason for it to
call handle_domain_irq().
Let's cement this split of responsibility and remove handle_domain_irq()
entirely, updating irqchip drivers to call generic_handle_domain_irq().
For consistency, handle_domain_nmi() is similarly removed and replaced
with a generic_handle_domain_nmi() function which also does not perform
any entry logic.
Previously handle_domain_{irq,nmi}() had a WARN_ON() which would fire
when they were called in an inappropriate context. So that we can
identify similar issues going forward, similar WARN_ON_ONCE() logic is
added to the generic_handle_*() functions, and comments are updated for
clarity and consistency.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
172 lines
3.8 KiB
C
172 lines
3.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2015 Dmitry Eremin-Solenikov
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* Copyright (C) 1999-2001 Nicolas Pitre
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*
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* Generic IRQ handling for the SA11x0.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/syscore_ops.h>
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#include <linux/irqchip/irq-sa11x0.h>
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#include <soc/sa1100/pwer.h>
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#include <asm/exception.h>
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#define ICIP 0x00 /* IC IRQ Pending reg. */
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#define ICMR 0x04 /* IC Mask Reg. */
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#define ICLR 0x08 /* IC Level Reg. */
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#define ICCR 0x0C /* IC Control Reg. */
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#define ICFP 0x10 /* IC FIQ Pending reg. */
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#define ICPR 0x20 /* IC Pending Reg. */
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static void __iomem *iobase;
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/*
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* We don't need to ACK IRQs on the SA1100 unless they're GPIOs
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* this is for internal IRQs i.e. from IRQ LCD to RTCAlrm.
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*/
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static void sa1100_mask_irq(struct irq_data *d)
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{
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u32 reg;
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reg = readl_relaxed(iobase + ICMR);
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reg &= ~BIT(d->hwirq);
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writel_relaxed(reg, iobase + ICMR);
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}
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static void sa1100_unmask_irq(struct irq_data *d)
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{
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u32 reg;
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reg = readl_relaxed(iobase + ICMR);
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reg |= BIT(d->hwirq);
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writel_relaxed(reg, iobase + ICMR);
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}
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static int sa1100_set_wake(struct irq_data *d, unsigned int on)
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{
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return sa11x0_sc_set_wake(d->hwirq, on);
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}
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static struct irq_chip sa1100_normal_chip = {
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.name = "SC",
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.irq_ack = sa1100_mask_irq,
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.irq_mask = sa1100_mask_irq,
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.irq_unmask = sa1100_unmask_irq,
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.irq_set_wake = sa1100_set_wake,
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};
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static int sa1100_normal_irqdomain_map(struct irq_domain *d,
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unsigned int irq, irq_hw_number_t hwirq)
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{
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irq_set_chip_and_handler(irq, &sa1100_normal_chip,
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handle_level_irq);
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return 0;
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}
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static const struct irq_domain_ops sa1100_normal_irqdomain_ops = {
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.map = sa1100_normal_irqdomain_map,
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.xlate = irq_domain_xlate_onetwocell,
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};
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static struct irq_domain *sa1100_normal_irqdomain;
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static struct sa1100irq_state {
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unsigned int saved;
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unsigned int icmr;
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unsigned int iclr;
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unsigned int iccr;
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} sa1100irq_state;
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static int sa1100irq_suspend(void)
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{
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struct sa1100irq_state *st = &sa1100irq_state;
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st->saved = 1;
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st->icmr = readl_relaxed(iobase + ICMR);
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st->iclr = readl_relaxed(iobase + ICLR);
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st->iccr = readl_relaxed(iobase + ICCR);
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/*
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* Disable all GPIO-based interrupts.
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*/
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writel_relaxed(st->icmr & 0xfffff000, iobase + ICMR);
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return 0;
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}
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static void sa1100irq_resume(void)
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{
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struct sa1100irq_state *st = &sa1100irq_state;
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if (st->saved) {
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writel_relaxed(st->iccr, iobase + ICCR);
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writel_relaxed(st->iclr, iobase + ICLR);
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writel_relaxed(st->icmr, iobase + ICMR);
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}
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}
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static struct syscore_ops sa1100irq_syscore_ops = {
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.suspend = sa1100irq_suspend,
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.resume = sa1100irq_resume,
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};
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static int __init sa1100irq_init_devicefs(void)
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{
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register_syscore_ops(&sa1100irq_syscore_ops);
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return 0;
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}
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device_initcall(sa1100irq_init_devicefs);
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static asmlinkage void __exception_irq_entry
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sa1100_handle_irq(struct pt_regs *regs)
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{
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uint32_t icip, icmr, mask;
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do {
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icip = readl_relaxed(iobase + ICIP);
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icmr = readl_relaxed(iobase + ICMR);
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mask = icip & icmr;
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if (mask == 0)
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break;
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generic_handle_domain_irq(sa1100_normal_irqdomain,
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ffs(mask) - 1);
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} while (1);
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}
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void __init sa11x0_init_irq_nodt(int irq_start, resource_size_t io_start)
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{
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iobase = ioremap(io_start, SZ_64K);
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if (WARN_ON(!iobase))
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return;
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/* disable all IRQs */
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writel_relaxed(0, iobase + ICMR);
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/* all IRQs are IRQ, not FIQ */
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writel_relaxed(0, iobase + ICLR);
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/*
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* Whatever the doc says, this has to be set for the wait-on-irq
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* instruction to work... on a SA1100 rev 9 at least.
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*/
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writel_relaxed(1, iobase + ICCR);
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sa1100_normal_irqdomain = irq_domain_add_simple(NULL,
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32, irq_start,
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&sa1100_normal_irqdomain_ops, NULL);
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set_handle_irq(sa1100_handle_irq);
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}
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