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This patch extends DAPM routing and adds secondary CPU DAI entry to support the secondary audio PCM interface on Odroid XU3. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
89 lines
2.0 KiB
Plaintext
89 lines
2.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Hardkernel Odroid XU3 audio subsystem device tree source
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*
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* Copyright (c) 2015 Krzysztof Kozlowski
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* Copyright (c) 2014 Collabora Ltd.
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* Copyright (c) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*/
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#include <dt-bindings/sound/samsung-i2s.h>
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/ {
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sound: sound {
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compatible = "samsung,odroid-xu3-audio";
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model = "Odroid-XU3";
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samsung,audio-widgets =
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"Headphone", "Headphone Jack",
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"Speakers", "Speakers";
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samsung,audio-routing =
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"Headphone Jack", "HPL",
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"Headphone Jack", "HPR",
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"Headphone Jack", "MICBIAS",
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"IN1", "Headphone Jack",
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"Speakers", "SPKL",
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"Speakers", "SPKR",
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"I2S Playback", "Mixer DAI TX",
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"HiFi Playback", "Mixer DAI TX";
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assigned-clocks = <&clock CLK_MOUT_EPLL>,
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<&clock CLK_MOUT_MAU_EPLL>,
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<&clock CLK_MOUT_USER_MAU_EPLL>,
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<&clock_audss EXYNOS_MOUT_AUDSS>,
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<&clock_audss EXYNOS_MOUT_I2S>,
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<&clock_audss EXYNOS_DOUT_SRP>,
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<&clock_audss EXYNOS_DOUT_AUD_BUS>,
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<&clock_audss EXYNOS_DOUT_I2S>;
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assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
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<&clock CLK_MOUT_EPLL>,
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<&clock CLK_MOUT_MAU_EPLL>,
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<&clock CLK_MAU_EPLL>,
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<&clock_audss EXYNOS_MOUT_AUDSS>;
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assigned-clock-rates = <0>,
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<0>,
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<0>,
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<0>,
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<0>,
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<196608001>,
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<(196608002 / 2)>,
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<196608000>;
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cpu {
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sound-dai = <&i2s0 0>, <&i2s0 1>;
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};
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codec {
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sound-dai = <&hdmi>, <&max98090>;
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};
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};
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};
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&clock_audss {
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assigned-clocks = <&clock_audss EXYNOS_DOUT_SRP>,
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<&clock CLK_FOUT_EPLL>;
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assigned-clock-rates = <(196608000 / 256)>,
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<196608000>;
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};
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&hsi2c_5 {
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status = "okay";
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max98090: max98090@10 {
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compatible = "maxim,max98090";
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reg = <0x10>;
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interrupt-parent = <&gpx3>;
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interrupts = <2 IRQ_TYPE_NONE>;
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clocks = <&i2s0 CLK_I2S_CDCLK>;
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clock-names = "mclk";
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#sound-dai-cells = <0>;
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};
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};
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&i2s0 {
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status = "okay";
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assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>;
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assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>;
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};
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