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cf973869b9
Since commit 8b41fc4454 ("kbuild: create modules.builtin without
Makefile.modbuiltin or tristate.conf"), MODULE_LICENSE declarations
are used to identify modules. As a consequence, uses of the macro
in non-modules will cause modprobe to misidentify their containing
object file as a module when it is not (false positives), and modprobe
might succeed rather than failing with a suitable error message.
So remove it in the files in this commit, none of which can be built as
modules.
Suggested-by: Luis Chamberlain <mcgrof@kernel.org>
Signed-off-by: Nick Alcock <nick.alcock@oracle.com>
Reviewed-by: Andy Shevchenko <andy@kernel.org>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20230224150811.80316-5-nick.alcock@oracle.com
276 lines
7.2 KiB
C
276 lines
7.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device access for Crystal Cove PMIC
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*
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* Copyright (C) 2012-2014, 2022 Intel Corporation. All rights reserved.
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*
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* Author: Yang, Bin <bin.yang@intel.com>
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* Author: Zhu, Lejun <lejun.zhu@linux.intel.com>
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*/
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/intel_soc_pmic.h>
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#include <linux/platform_data/x86/soc.h>
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#include <linux/pwm.h>
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#include <linux/regmap.h>
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#define CRYSTAL_COVE_MAX_REGISTER 0xC6
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#define CRYSTAL_COVE_REG_IRQLVL1 0x02
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#define CRYSTAL_COVE_REG_MIRQLVL1 0x0E
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#define CRYSTAL_COVE_IRQ_PWRSRC 0
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#define CRYSTAL_COVE_IRQ_THRM 1
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#define CRYSTAL_COVE_IRQ_BCU 2
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#define CRYSTAL_COVE_IRQ_ADC 3
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#define CRYSTAL_COVE_IRQ_CHGR 4
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#define CRYSTAL_COVE_IRQ_GPIO 5
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#define CRYSTAL_COVE_IRQ_VHDMIOCP 6
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static const struct resource pwrsrc_resources[] = {
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DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_PWRSRC, "PWRSRC"),
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};
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static const struct resource thermal_resources[] = {
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DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_THRM, "THERMAL"),
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};
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static const struct resource bcu_resources[] = {
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DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_BCU, "BCU"),
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};
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static const struct resource adc_resources[] = {
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DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_ADC, "ADC"),
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};
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static const struct resource charger_resources[] = {
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DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_CHGR, "CHGR"),
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};
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static const struct resource gpio_resources[] = {
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DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_GPIO, "GPIO"),
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};
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static struct mfd_cell crystal_cove_byt_dev[] = {
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{
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.name = "crystal_cove_pwrsrc",
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.num_resources = ARRAY_SIZE(pwrsrc_resources),
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.resources = pwrsrc_resources,
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},
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{
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.name = "crystal_cove_thermal",
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.num_resources = ARRAY_SIZE(thermal_resources),
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.resources = thermal_resources,
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},
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{
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.name = "crystal_cove_bcu",
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.num_resources = ARRAY_SIZE(bcu_resources),
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.resources = bcu_resources,
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},
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{
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.name = "crystal_cove_adc",
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.num_resources = ARRAY_SIZE(adc_resources),
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.resources = adc_resources,
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},
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{
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.name = "crystal_cove_charger",
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.num_resources = ARRAY_SIZE(charger_resources),
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.resources = charger_resources,
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},
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{
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.name = "crystal_cove_gpio",
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.num_resources = ARRAY_SIZE(gpio_resources),
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.resources = gpio_resources,
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},
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{
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.name = "byt_crystal_cove_pmic",
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},
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{
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.name = "crystal_cove_pwm",
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},
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};
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static struct mfd_cell crystal_cove_cht_dev[] = {
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{
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.name = "crystal_cove_gpio",
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.num_resources = ARRAY_SIZE(gpio_resources),
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.resources = gpio_resources,
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},
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{
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.name = "cht_crystal_cove_pmic",
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},
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{
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.name = "crystal_cove_pwm",
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},
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};
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static const struct regmap_config crystal_cove_regmap_config = {
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.reg_bits = 8,
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.val_bits = 8,
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.max_register = CRYSTAL_COVE_MAX_REGISTER,
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.cache_type = REGCACHE_NONE,
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};
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static const struct regmap_irq crystal_cove_irqs[] = {
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REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_PWRSRC, 0, BIT(CRYSTAL_COVE_IRQ_PWRSRC)),
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REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_THRM, 0, BIT(CRYSTAL_COVE_IRQ_THRM)),
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REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_BCU, 0, BIT(CRYSTAL_COVE_IRQ_BCU)),
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REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_ADC, 0, BIT(CRYSTAL_COVE_IRQ_ADC)),
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REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_CHGR, 0, BIT(CRYSTAL_COVE_IRQ_CHGR)),
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REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_GPIO, 0, BIT(CRYSTAL_COVE_IRQ_GPIO)),
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REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_VHDMIOCP, 0, BIT(CRYSTAL_COVE_IRQ_VHDMIOCP)),
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};
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static const struct regmap_irq_chip crystal_cove_irq_chip = {
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.name = "Crystal Cove",
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.irqs = crystal_cove_irqs,
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.num_irqs = ARRAY_SIZE(crystal_cove_irqs),
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.num_regs = 1,
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.status_base = CRYSTAL_COVE_REG_IRQLVL1,
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.mask_base = CRYSTAL_COVE_REG_MIRQLVL1,
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};
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/* PWM consumed by the Intel GFX */
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static struct pwm_lookup crc_pwm_lookup[] = {
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PWM_LOOKUP("crystal_cove_pwm", 0, "0000:00:02.0", "pwm_pmic_backlight", 0, PWM_POLARITY_NORMAL),
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};
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struct crystal_cove_config {
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unsigned long irq_flags;
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struct mfd_cell *cell_dev;
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int n_cell_devs;
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const struct regmap_config *regmap_config;
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const struct regmap_irq_chip *irq_chip;
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};
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static const struct crystal_cove_config crystal_cove_config_byt_crc = {
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.irq_flags = IRQF_TRIGGER_RISING,
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.cell_dev = crystal_cove_byt_dev,
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.n_cell_devs = ARRAY_SIZE(crystal_cove_byt_dev),
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.regmap_config = &crystal_cove_regmap_config,
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.irq_chip = &crystal_cove_irq_chip,
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};
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static const struct crystal_cove_config crystal_cove_config_cht_crc = {
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.irq_flags = IRQF_TRIGGER_RISING,
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.cell_dev = crystal_cove_cht_dev,
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.n_cell_devs = ARRAY_SIZE(crystal_cove_cht_dev),
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.regmap_config = &crystal_cove_regmap_config,
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.irq_chip = &crystal_cove_irq_chip,
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};
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static int crystal_cove_i2c_probe(struct i2c_client *i2c)
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{
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const struct crystal_cove_config *config;
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struct device *dev = &i2c->dev;
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struct intel_soc_pmic *pmic;
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int ret;
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if (soc_intel_is_byt())
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config = &crystal_cove_config_byt_crc;
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else
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config = &crystal_cove_config_cht_crc;
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pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);
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if (!pmic)
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return -ENOMEM;
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i2c_set_clientdata(i2c, pmic);
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pmic->regmap = devm_regmap_init_i2c(i2c, config->regmap_config);
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if (IS_ERR(pmic->regmap))
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return PTR_ERR(pmic->regmap);
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pmic->irq = i2c->irq;
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ret = devm_regmap_add_irq_chip(dev, pmic->regmap, pmic->irq,
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config->irq_flags | IRQF_ONESHOT,
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0, config->irq_chip, &pmic->irq_chip_data);
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if (ret)
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return ret;
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ret = enable_irq_wake(pmic->irq);
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if (ret)
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dev_warn(dev, "Can't enable IRQ as wake source: %d\n", ret);
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/* Add lookup table for crc-pwm */
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pwm_add_table(crc_pwm_lookup, ARRAY_SIZE(crc_pwm_lookup));
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/* To distuingish this domain from the GPIO/charger's irqchip domains */
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irq_domain_update_bus_token(regmap_irq_get_domain(pmic->irq_chip_data),
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DOMAIN_BUS_NEXUS);
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ret = mfd_add_devices(dev, PLATFORM_DEVID_NONE, config->cell_dev,
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config->n_cell_devs, NULL, 0,
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regmap_irq_get_domain(pmic->irq_chip_data));
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if (ret)
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pwm_remove_table(crc_pwm_lookup, ARRAY_SIZE(crc_pwm_lookup));
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return ret;
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}
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static void crystal_cove_i2c_remove(struct i2c_client *i2c)
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{
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/* remove crc-pwm lookup table */
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pwm_remove_table(crc_pwm_lookup, ARRAY_SIZE(crc_pwm_lookup));
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mfd_remove_devices(&i2c->dev);
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}
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static void crystal_cove_shutdown(struct i2c_client *i2c)
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{
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struct intel_soc_pmic *pmic = i2c_get_clientdata(i2c);
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disable_irq(pmic->irq);
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return;
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}
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static int crystal_cove_suspend(struct device *dev)
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{
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struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
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disable_irq(pmic->irq);
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return 0;
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}
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static int crystal_cove_resume(struct device *dev)
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{
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struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
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enable_irq(pmic->irq);
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return 0;
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}
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static DEFINE_SIMPLE_DEV_PM_OPS(crystal_cove_pm_ops, crystal_cove_suspend, crystal_cove_resume);
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static const struct acpi_device_id crystal_cove_acpi_match[] = {
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{ "INT33FD" },
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{ },
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};
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MODULE_DEVICE_TABLE(acpi, crystal_cove_acpi_match);
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static struct i2c_driver crystal_cove_i2c_driver = {
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.driver = {
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.name = "crystal_cove_i2c",
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.pm = pm_sleep_ptr(&crystal_cove_pm_ops),
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.acpi_match_table = crystal_cove_acpi_match,
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},
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.probe_new = crystal_cove_i2c_probe,
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.remove = crystal_cove_i2c_remove,
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.shutdown = crystal_cove_shutdown,
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};
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module_i2c_driver(crystal_cove_i2c_driver);
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MODULE_DESCRIPTION("I2C driver for Intel SoC PMIC");
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MODULE_AUTHOR("Yang, Bin <bin.yang@intel.com>");
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MODULE_AUTHOR("Zhu, Lejun <lejun.zhu@linux.intel.com>");
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