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Some Intel processors may use alternate predictors for RETs on RSB-underflow. This condition may be vulnerable to Branch History Injection (BHI) and intramode-BTI. Kernel earlier added spectre_v2 mitigation modes (eIBRS+Retpolines, eIBRS+LFENCE, Retpolines) which protect indirect CALLs and JMPs against such attacks. However, on RSB-underflow, RET target prediction may fallback to alternate predictors. As a result, RET's predicted target may get influenced by branch history. A new MSR_IA32_SPEC_CTRL bit (RRSBA_DIS_S) controls this fallback behavior when in kernel mode. When set, RETs will not take predictions from alternate predictors, hence mitigating RETs as well. Support for this is enumerated by CPUID.7.2.EDX[RRSBA_CTRL] (bit2). For spectre v2 mitigation, when a user selects a mitigation that protects indirect CALLs and JMPs against BHI and intramode-BTI, set RRSBA_DIS_S also to protect RETs for RSB-underflow case. Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com> Signed-off-by: Borislav Petkov <bp@suse.de> |
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| alpha/include | ||
| arc/include/uapi/asm | ||
| arm/include | ||
| arm64/include | ||
| csky/include/uapi/asm | ||
| hexagon/include/uapi/asm | ||
| ia64/include | ||
| microblaze/include/uapi/asm | ||
| mips/include | ||
| parisc/include/uapi/asm | ||
| powerpc/include | ||
| riscv/include/uapi/asm | ||
| s390/include | ||
| sh/include | ||
| sparc/include | ||
| x86 | ||
| xtensa/include | ||