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Future uapi needs to give userspace the ability to select the pat_index for a given vm_bind. However we need to be able to extract the coherency mode from the provided pat_index to ensure it's compatible with the cpu_caching mode set at object creation. There are various security reasons for why this matters. However the pat_index itself is very platform specific, so seems reasonable to annotate each platform definition of the pat table. On some older platforms there is no explicit coherency mode, so we just pick whatever makes sense. v2: - Simplify with COH_AT_LEAST_1_WAY - Add some kernel-doc v3 (Matt Roper): - Some small tweaks v4: - Rebase v5: - Rebase on Xe2 PAT additions v6: - Rebase on removal of coh_mode from uapi Bspec: 45101, 44235 #xe Bspec: 70552, 71582, 59400 #xe2 Signed-off-by: Matthew Auld <matthew.auld@intel.com> Cc: Pallavi Mishra <pallavi.mishra@intel.com> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Filip Hazubski <filip.hazubski@intel.com> Cc: Carl Zhang <carl.zhang@intel.com> Cc: Effie Yu <effie.yu@intel.com> Cc: Zhengguo Xu <zhengguo.xu@intel.com> Cc: Francois Dugast <francois.dugast@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Pallavi Mishra <pallavi.mishra@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
62 lines
1.3 KiB
C
62 lines
1.3 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef _XE_PAT_H_
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#define _XE_PAT_H_
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#include <linux/types.h>
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struct drm_printer;
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struct xe_device;
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struct xe_gt;
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/**
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* struct xe_pat_table_entry - The pat_index encoding and other meta information.
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*/
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struct xe_pat_table_entry {
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/**
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* @value: The platform specific value encoding the various memory
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* attributes (this maps to some fixed pat_index). So things like
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* caching, coherency, compression etc can be encoded here.
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*/
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u32 value;
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/**
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* @coh_mode: The GPU coherency mode that @value maps to.
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*/
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#define XE_COH_NONE 1
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#define XE_COH_AT_LEAST_1WAY 2
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u16 coh_mode;
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};
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/**
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* xe_pat_init_early - SW initialization, setting up data based on device
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* @xe: xe device
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*/
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void xe_pat_init_early(struct xe_device *xe);
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/**
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* xe_pat_init - Program HW PAT table
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* @gt: GT structure
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*/
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void xe_pat_init(struct xe_gt *gt);
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/**
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* xe_pat_dump - Dump PAT table
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* @gt: GT structure
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* @p: Printer to dump info to
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*/
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void xe_pat_dump(struct xe_gt *gt, struct drm_printer *p);
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/**
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* xe_pat_index_get_coh_mode - Extract the coherency mode for the given
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* pat_index.
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* @xe: xe device
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* @pat_index: The pat_index to query
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*/
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u16 xe_pat_index_get_coh_mode(struct xe_device *xe, u16 pat_index);
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#endif
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