Mika Kuoppala 4aa0b5d457 drm/i915/tgl: Add HDC Pipeline Flush ... Add hdc pipeline flush to ensure memory state is coherent in L3 when we are done. v2: Flush also in breadcrumbs (Chris) Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20191015154449.10338-3-mika.kuoppala@linux.intel.com		2019-10-15 18:15:59 +01:00
..
drm	drm/i915/tgl: Add HDC Pipeline Flush	2019-10-15 18:15:59 +01:00
host1x	drm/tegra: Changes for v5.3-rc1	2019-06-25 12:59:43 +10:00
ipu-v3	gpu: ipu-v3: image-convert: only sample into the next tile if necessary	2019-08-19 16:25:30 +02:00
vga	topic/remove-fbcon-notifiers:	2019-06-26 12:26:34 +02:00
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