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e3b85b0765
a lot of developers were on holidays (including myself) it was a good timing to apply lots of cleanups which would normally cause merge conflicts with other floating patches. Extra thanks go to Andi Shyti who backed me up when I was on a four week hiatus. This is also the reason that some patches were commited later than ideal. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEOZGx6rniZ1Gk92RdFA3kzBSgKbYFAmT1wHkACgkQFA3kzBSg KbYwEBAAohvOqMh7OrwkIHATzjJxHNKPZ0USky5DVURTWLTGG4GDD9Mc7/Ft+lvz 7ifzf3yDLbaZUGQMVA7FqV7tfJu/kT7TGjAX7Jf9hf148TAQtkcyKGe/JfJW9Xtt I1rETXdB1YOABni9aMpH6mpyFKxQbgwpx/4bLs6or0gdy34qIm8FLhuDnkKZF9bO mERVDfAqcASP33XqF8EoOQYYh+7lyCmtqwzfFGqwXHnUPTMiD3fjkj4pJ9zx/0V2 fQh5KeoqEm1m3mctNQ2HhljmVZjrp1VASsDPA0Y+8yqUHqB8RtMSnL57d420IGdg zCuiXYK918KfwUtgWhTRUOmA8TrqSntBrKEaqN92SNXc5+LQ+ASICwvgapfVWmTM OixrBSBjkcQzaSwQOgXosqmwSeH0GS8646mIVMj/GPvmkG4bSmAWmSZX+Nuw58ZN cGxSLX7lJyx3LCIZUFe2ge0rngOHt1fdKL1lS4ISiVO9w4r/HZQdStIWk5JD+Kls mNM6an5l5SLEJ89h3Q4MQP2sQpuHOU4awBmuGmDEPlFlvYYt4P8r1eoD373SYFH5 oF6DTfjDulg3rxFAV9sOQvgbQ2PyiYfuz09TikcYX1TyJ0iFAbWQQMCQ6HqjgoDs PA9ghXUlOYjKWIsznZ5fR0ySUM47LDkyoIfBS3Bk66z7Sbtl0J8= =gpYJ -----END PGP SIGNATURE----- Merge tag 'i2c-for-6.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux Pull i2c updates from Wolfram Sang: "I2C has mainly cleanups this time and a few driver improvements. Because a lot of developers were on holidays (including myself) it was a good timing to apply lots of cleanups which would normally cause merge conflicts with other floating patches. Extra thanks go to Andi Shyti who backed me up when I was on a four week hiatus. This is also the reason that some patches were commited later than ideal" * tag 'i2c-for-6.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: (67 commits) i2c: at91: Use dev_err_probe() instead of dev_err() I2C: ali15x3: Do PCI error checks on own line i2c: Make return value check more accurate and explicit for devm_pinctrl_get() i2c: designware: Add support for recovery when GPIO need pinctrl i2c: mlxcpld: Add support for extended transaction length i2c: mlxcpld: Allow driver to run on ARM64 architecture i2c: nforce2: Do PCI error check on own line i2c: sis5595: Do PCI error checks on own line i2c: qcom-cci: Fix error checking in cci_probe() i2c: muxes: pca954x: Add regulator support i2c: muxes: pca954x: Add MAX735x/MAX736x support dt-bindings: i2c: Add Maxim MAX735x/MAX736x variants dt-bindings: i2c: pca954x: Correct interrupt support i2c: pnx: Use devm_platform_get_and_ioremap_resource() i2c: pxa: Use devm_platform_get_and_ioremap_resource() i2c: s3c2410: Use devm_platform_get_and_ioremap_resource() i2c: sh_mobile: Use devm_platform_get_and_ioremap_resource() i2c: st: Use devm_platform_get_and_ioremap_resource() i2c: qcom-geni: Convert to devm_platform_ioremap_resource() i2c: stm32f4: Use devm_platform_get_and_ioremap_resource() ...
1069 lines
28 KiB
C
1069 lines
28 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Synopsys DesignWare I2C adapter driver (master only).
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*
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* Based on the TI DAVINCI I2C adapter driver.
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*
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* Copyright (C) 2006 Texas Instruments.
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* Copyright (C) 2007 MontaVista Software Inc.
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* Copyright (C) 2009 Provigent Ltd.
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*/
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/export.h>
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#include <linux/gpio/consumer.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include "i2c-designware-core.h"
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#define AMD_TIMEOUT_MIN_US 25
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#define AMD_TIMEOUT_MAX_US 250
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#define AMD_MASTERCFG_MASK GENMASK(15, 0)
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static void i2c_dw_configure_fifo_master(struct dw_i2c_dev *dev)
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{
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/* Configure Tx/Rx FIFO threshold levels */
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regmap_write(dev->map, DW_IC_TX_TL, dev->tx_fifo_depth / 2);
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regmap_write(dev->map, DW_IC_RX_TL, 0);
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/* Configure the I2C master */
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regmap_write(dev->map, DW_IC_CON, dev->master_cfg);
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}
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static int i2c_dw_set_timings_master(struct dw_i2c_dev *dev)
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{
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unsigned int comp_param1;
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u32 sda_falling_time, scl_falling_time;
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struct i2c_timings *t = &dev->timings;
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const char *fp_str = "";
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u32 ic_clk;
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int ret;
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ret = i2c_dw_acquire_lock(dev);
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if (ret)
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return ret;
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ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, &comp_param1);
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i2c_dw_release_lock(dev);
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if (ret)
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return ret;
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/* Set standard and fast speed dividers for high/low periods */
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sda_falling_time = t->sda_fall_ns ?: 300; /* ns */
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scl_falling_time = t->scl_fall_ns ?: 300; /* ns */
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/* Calculate SCL timing parameters for standard mode if not set */
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if (!dev->ss_hcnt || !dev->ss_lcnt) {
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ic_clk = i2c_dw_clk_rate(dev);
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dev->ss_hcnt =
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i2c_dw_scl_hcnt(ic_clk,
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4000, /* tHD;STA = tHIGH = 4.0 us */
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sda_falling_time,
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0, /* 0: DW default, 1: Ideal */
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0); /* No offset */
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dev->ss_lcnt =
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i2c_dw_scl_lcnt(ic_clk,
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4700, /* tLOW = 4.7 us */
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scl_falling_time,
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0); /* No offset */
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}
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dev_dbg(dev->dev, "Standard Mode HCNT:LCNT = %d:%d\n",
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dev->ss_hcnt, dev->ss_lcnt);
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/*
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* Set SCL timing parameters for fast mode or fast mode plus. Only
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* difference is the timing parameter values since the registers are
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* the same.
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*/
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if (t->bus_freq_hz == I2C_MAX_FAST_MODE_PLUS_FREQ) {
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/*
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* Check are Fast Mode Plus parameters available. Calculate
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* SCL timing parameters for Fast Mode Plus if not set.
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*/
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if (dev->fp_hcnt && dev->fp_lcnt) {
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dev->fs_hcnt = dev->fp_hcnt;
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dev->fs_lcnt = dev->fp_lcnt;
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} else {
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ic_clk = i2c_dw_clk_rate(dev);
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dev->fs_hcnt =
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i2c_dw_scl_hcnt(ic_clk,
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260, /* tHIGH = 260 ns */
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sda_falling_time,
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0, /* DW default */
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0); /* No offset */
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dev->fs_lcnt =
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i2c_dw_scl_lcnt(ic_clk,
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500, /* tLOW = 500 ns */
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scl_falling_time,
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0); /* No offset */
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}
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fp_str = " Plus";
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}
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/*
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* Calculate SCL timing parameters for fast mode if not set. They are
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* needed also in high speed mode.
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*/
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if (!dev->fs_hcnt || !dev->fs_lcnt) {
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ic_clk = i2c_dw_clk_rate(dev);
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dev->fs_hcnt =
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i2c_dw_scl_hcnt(ic_clk,
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600, /* tHD;STA = tHIGH = 0.6 us */
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sda_falling_time,
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0, /* 0: DW default, 1: Ideal */
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0); /* No offset */
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dev->fs_lcnt =
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i2c_dw_scl_lcnt(ic_clk,
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1300, /* tLOW = 1.3 us */
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scl_falling_time,
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0); /* No offset */
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}
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dev_dbg(dev->dev, "Fast Mode%s HCNT:LCNT = %d:%d\n",
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fp_str, dev->fs_hcnt, dev->fs_lcnt);
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/* Check is high speed possible and fall back to fast mode if not */
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if ((dev->master_cfg & DW_IC_CON_SPEED_MASK) ==
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DW_IC_CON_SPEED_HIGH) {
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if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)
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!= DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH) {
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dev_err(dev->dev, "High Speed not supported!\n");
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t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ;
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dev->master_cfg &= ~DW_IC_CON_SPEED_MASK;
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dev->master_cfg |= DW_IC_CON_SPEED_FAST;
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dev->hs_hcnt = 0;
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dev->hs_lcnt = 0;
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} else if (!dev->hs_hcnt || !dev->hs_lcnt) {
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ic_clk = i2c_dw_clk_rate(dev);
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dev->hs_hcnt =
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i2c_dw_scl_hcnt(ic_clk,
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160, /* tHIGH = 160 ns */
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sda_falling_time,
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0, /* DW default */
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0); /* No offset */
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dev->hs_lcnt =
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i2c_dw_scl_lcnt(ic_clk,
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320, /* tLOW = 320 ns */
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scl_falling_time,
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0); /* No offset */
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}
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dev_dbg(dev->dev, "High Speed Mode HCNT:LCNT = %d:%d\n",
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dev->hs_hcnt, dev->hs_lcnt);
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}
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ret = i2c_dw_set_sda_hold(dev);
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if (ret)
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return ret;
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dev_dbg(dev->dev, "Bus speed: %s\n", i2c_freq_mode_string(t->bus_freq_hz));
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return 0;
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}
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/**
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* i2c_dw_init_master() - Initialize the designware I2C master hardware
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* @dev: device private data
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*
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* This functions configures and enables the I2C master.
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* This function is called during I2C init function, and in case of timeout at
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* run time.
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*/
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static int i2c_dw_init_master(struct dw_i2c_dev *dev)
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{
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int ret;
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ret = i2c_dw_acquire_lock(dev);
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if (ret)
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return ret;
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/* Disable the adapter */
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__i2c_dw_disable(dev);
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/* Write standard speed timing parameters */
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regmap_write(dev->map, DW_IC_SS_SCL_HCNT, dev->ss_hcnt);
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regmap_write(dev->map, DW_IC_SS_SCL_LCNT, dev->ss_lcnt);
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/* Write fast mode/fast mode plus timing parameters */
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regmap_write(dev->map, DW_IC_FS_SCL_HCNT, dev->fs_hcnt);
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regmap_write(dev->map, DW_IC_FS_SCL_LCNT, dev->fs_lcnt);
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/* Write high speed timing parameters if supported */
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if (dev->hs_hcnt && dev->hs_lcnt) {
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regmap_write(dev->map, DW_IC_HS_SCL_HCNT, dev->hs_hcnt);
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regmap_write(dev->map, DW_IC_HS_SCL_LCNT, dev->hs_lcnt);
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}
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/* Write SDA hold time if supported */
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if (dev->sda_hold_time)
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regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time);
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i2c_dw_configure_fifo_master(dev);
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i2c_dw_release_lock(dev);
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return 0;
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}
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static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
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{
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struct i2c_msg *msgs = dev->msgs;
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u32 ic_con = 0, ic_tar = 0;
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unsigned int dummy;
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/* Disable the adapter */
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__i2c_dw_disable(dev);
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/* If the slave address is ten bit address, enable 10BITADDR */
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if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) {
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ic_con = DW_IC_CON_10BITADDR_MASTER;
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/*
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* If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing
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* mode has to be enabled via bit 12 of IC_TAR register.
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* We set it always as I2C_DYNAMIC_TAR_UPDATE can't be
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* detected from registers.
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*/
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ic_tar = DW_IC_TAR_10BITADDR_MASTER;
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}
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regmap_update_bits(dev->map, DW_IC_CON, DW_IC_CON_10BITADDR_MASTER,
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ic_con);
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/*
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* Set the slave (target) address and enable 10-bit addressing mode
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* if applicable.
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*/
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regmap_write(dev->map, DW_IC_TAR,
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msgs[dev->msg_write_idx].addr | ic_tar);
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/* Enforce disabled interrupts (due to HW issues) */
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regmap_write(dev->map, DW_IC_INTR_MASK, 0);
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/* Enable the adapter */
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__i2c_dw_enable(dev);
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/* Dummy read to avoid the register getting stuck on Bay Trail */
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regmap_read(dev->map, DW_IC_ENABLE_STATUS, &dummy);
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/* Clear and enable interrupts */
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regmap_read(dev->map, DW_IC_CLR_INTR, &dummy);
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regmap_write(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_MASTER_MASK);
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}
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static int i2c_dw_check_stopbit(struct dw_i2c_dev *dev)
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{
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u32 val;
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int ret;
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ret = regmap_read_poll_timeout(dev->map, DW_IC_INTR_STAT, val,
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!(val & DW_IC_INTR_STOP_DET),
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1100, 20000);
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if (ret)
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dev_err(dev->dev, "i2c timeout error %d\n", ret);
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return ret;
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}
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static int i2c_dw_status(struct dw_i2c_dev *dev)
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{
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int status;
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status = i2c_dw_wait_bus_not_busy(dev);
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if (status)
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return status;
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return i2c_dw_check_stopbit(dev);
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}
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/*
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* Initiate and continue master read/write transaction with polling
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* based transfer routine afterward write messages into the Tx buffer.
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*/
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static int amd_i2c_dw_xfer_quirk(struct i2c_adapter *adap, struct i2c_msg *msgs, int num_msgs)
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{
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struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
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int msg_wrt_idx, msg_itr_lmt, buf_len, data_idx;
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int cmd = 0, status;
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u8 *tx_buf;
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unsigned int val;
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/*
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* In order to enable the interrupt for UCSI i.e. AMD NAVI GPU card,
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* it is mandatory to set the right value in specific register
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* (offset:0x474) as per the hardware IP specification.
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*/
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regmap_write(dev->map, AMD_UCSI_INTR_REG, AMD_UCSI_INTR_EN);
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dev->msgs = msgs;
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dev->msgs_num = num_msgs;
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i2c_dw_xfer_init(dev);
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regmap_write(dev->map, DW_IC_INTR_MASK, 0);
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/* Initiate messages read/write transaction */
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for (msg_wrt_idx = 0; msg_wrt_idx < num_msgs; msg_wrt_idx++) {
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tx_buf = msgs[msg_wrt_idx].buf;
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buf_len = msgs[msg_wrt_idx].len;
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if (!(msgs[msg_wrt_idx].flags & I2C_M_RD))
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regmap_write(dev->map, DW_IC_TX_TL, buf_len - 1);
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/*
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* Initiate the i2c read/write transaction of buffer length,
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* and poll for bus busy status. For the last message transfer,
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* update the command with stopbit enable.
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*/
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for (msg_itr_lmt = buf_len; msg_itr_lmt > 0; msg_itr_lmt--) {
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if (msg_wrt_idx == num_msgs - 1 && msg_itr_lmt == 1)
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cmd |= BIT(9);
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if (msgs[msg_wrt_idx].flags & I2C_M_RD) {
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/* Due to hardware bug, need to write the same command twice. */
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regmap_write(dev->map, DW_IC_DATA_CMD, 0x100);
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regmap_write(dev->map, DW_IC_DATA_CMD, 0x100 | cmd);
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if (cmd) {
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regmap_write(dev->map, DW_IC_TX_TL, 2 * (buf_len - 1));
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regmap_write(dev->map, DW_IC_RX_TL, 2 * (buf_len - 1));
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/*
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* Need to check the stop bit. However, it cannot be
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* detected from the registers so we check it always
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* when read/write the last byte.
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*/
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status = i2c_dw_status(dev);
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if (status)
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return status;
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for (data_idx = 0; data_idx < buf_len; data_idx++) {
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regmap_read(dev->map, DW_IC_DATA_CMD, &val);
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tx_buf[data_idx] = val;
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}
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status = i2c_dw_check_stopbit(dev);
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if (status)
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return status;
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}
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} else {
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regmap_write(dev->map, DW_IC_DATA_CMD, *tx_buf++ | cmd);
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usleep_range(AMD_TIMEOUT_MIN_US, AMD_TIMEOUT_MAX_US);
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}
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}
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status = i2c_dw_check_stopbit(dev);
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if (status)
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return status;
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}
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return 0;
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}
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static int i2c_dw_poll_tx_empty(struct dw_i2c_dev *dev)
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{
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u32 val;
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return regmap_read_poll_timeout(dev->map, DW_IC_RAW_INTR_STAT, val,
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val & DW_IC_INTR_TX_EMPTY,
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100, 1000);
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}
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static int i2c_dw_poll_rx_full(struct dw_i2c_dev *dev)
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{
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u32 val;
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return regmap_read_poll_timeout(dev->map, DW_IC_RAW_INTR_STAT, val,
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val & DW_IC_INTR_RX_FULL,
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100, 1000);
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}
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static int txgbe_i2c_dw_xfer_quirk(struct i2c_adapter *adap, struct i2c_msg *msgs,
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int num_msgs)
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{
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struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
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int msg_idx, buf_len, data_idx, ret;
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unsigned int val, stop = 0;
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u8 *buf;
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dev->msgs = msgs;
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dev->msgs_num = num_msgs;
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i2c_dw_xfer_init(dev);
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regmap_write(dev->map, DW_IC_INTR_MASK, 0);
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|
|
for (msg_idx = 0; msg_idx < num_msgs; msg_idx++) {
|
|
buf = msgs[msg_idx].buf;
|
|
buf_len = msgs[msg_idx].len;
|
|
|
|
for (data_idx = 0; data_idx < buf_len; data_idx++) {
|
|
if (msg_idx == num_msgs - 1 && data_idx == buf_len - 1)
|
|
stop |= BIT(9);
|
|
|
|
if (msgs[msg_idx].flags & I2C_M_RD) {
|
|
regmap_write(dev->map, DW_IC_DATA_CMD, 0x100 | stop);
|
|
|
|
ret = i2c_dw_poll_rx_full(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
regmap_read(dev->map, DW_IC_DATA_CMD, &val);
|
|
buf[data_idx] = val;
|
|
} else {
|
|
ret = i2c_dw_poll_tx_empty(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
regmap_write(dev->map, DW_IC_DATA_CMD,
|
|
buf[data_idx] | stop);
|
|
}
|
|
}
|
|
}
|
|
|
|
return num_msgs;
|
|
}
|
|
|
|
/*
|
|
* Initiate (and continue) low level master read/write transaction.
|
|
* This function is only called from i2c_dw_isr, and pumping i2c_msg
|
|
* messages into the tx buffer. Even if the size of i2c_msg data is
|
|
* longer than the size of the tx buffer, it handles everything.
|
|
*/
|
|
static void
|
|
i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
|
|
{
|
|
struct i2c_msg *msgs = dev->msgs;
|
|
u32 intr_mask;
|
|
int tx_limit, rx_limit;
|
|
u32 addr = msgs[dev->msg_write_idx].addr;
|
|
u32 buf_len = dev->tx_buf_len;
|
|
u8 *buf = dev->tx_buf;
|
|
bool need_restart = false;
|
|
unsigned int flr;
|
|
|
|
intr_mask = DW_IC_INTR_MASTER_MASK;
|
|
|
|
for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
|
|
u32 flags = msgs[dev->msg_write_idx].flags;
|
|
|
|
/*
|
|
* If target address has changed, we need to
|
|
* reprogram the target address in the I2C
|
|
* adapter when we are done with this transfer.
|
|
*/
|
|
if (msgs[dev->msg_write_idx].addr != addr) {
|
|
dev_err(dev->dev,
|
|
"%s: invalid target address\n", __func__);
|
|
dev->msg_err = -EINVAL;
|
|
break;
|
|
}
|
|
|
|
if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
|
|
/* new i2c_msg */
|
|
buf = msgs[dev->msg_write_idx].buf;
|
|
buf_len = msgs[dev->msg_write_idx].len;
|
|
|
|
/* If both IC_EMPTYFIFO_HOLD_MASTER_EN and
|
|
* IC_RESTART_EN are set, we must manually
|
|
* set restart bit between messages.
|
|
*/
|
|
if ((dev->master_cfg & DW_IC_CON_RESTART_EN) &&
|
|
(dev->msg_write_idx > 0))
|
|
need_restart = true;
|
|
}
|
|
|
|
regmap_read(dev->map, DW_IC_TXFLR, &flr);
|
|
tx_limit = dev->tx_fifo_depth - flr;
|
|
|
|
regmap_read(dev->map, DW_IC_RXFLR, &flr);
|
|
rx_limit = dev->rx_fifo_depth - flr;
|
|
|
|
while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
|
|
u32 cmd = 0;
|
|
|
|
/*
|
|
* If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must
|
|
* manually set the stop bit. However, it cannot be
|
|
* detected from the registers so we set it always
|
|
* when writing/reading the last byte.
|
|
*/
|
|
|
|
/*
|
|
* i2c-core always sets the buffer length of
|
|
* I2C_FUNC_SMBUS_BLOCK_DATA to 1. The length will
|
|
* be adjusted when receiving the first byte.
|
|
* Thus we can't stop the transaction here.
|
|
*/
|
|
if (dev->msg_write_idx == dev->msgs_num - 1 &&
|
|
buf_len == 1 && !(flags & I2C_M_RECV_LEN))
|
|
cmd |= BIT(9);
|
|
|
|
if (need_restart) {
|
|
cmd |= BIT(10);
|
|
need_restart = false;
|
|
}
|
|
|
|
if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
|
|
|
|
/* Avoid rx buffer overrun */
|
|
if (dev->rx_outstanding >= dev->rx_fifo_depth)
|
|
break;
|
|
|
|
regmap_write(dev->map, DW_IC_DATA_CMD,
|
|
cmd | 0x100);
|
|
rx_limit--;
|
|
dev->rx_outstanding++;
|
|
} else {
|
|
regmap_write(dev->map, DW_IC_DATA_CMD,
|
|
cmd | *buf++);
|
|
}
|
|
tx_limit--; buf_len--;
|
|
}
|
|
|
|
dev->tx_buf = buf;
|
|
dev->tx_buf_len = buf_len;
|
|
|
|
/*
|
|
* Because we don't know the buffer length in the
|
|
* I2C_FUNC_SMBUS_BLOCK_DATA case, we can't stop
|
|
* the transaction here.
|
|
*/
|
|
if (buf_len > 0 || flags & I2C_M_RECV_LEN) {
|
|
/* more bytes to be written */
|
|
dev->status |= STATUS_WRITE_IN_PROGRESS;
|
|
break;
|
|
} else
|
|
dev->status &= ~STATUS_WRITE_IN_PROGRESS;
|
|
}
|
|
|
|
/*
|
|
* If i2c_msg index search is completed, we don't need TX_EMPTY
|
|
* interrupt any more.
|
|
*/
|
|
if (dev->msg_write_idx == dev->msgs_num)
|
|
intr_mask &= ~DW_IC_INTR_TX_EMPTY;
|
|
|
|
if (dev->msg_err)
|
|
intr_mask = 0;
|
|
|
|
regmap_write(dev->map, DW_IC_INTR_MASK, intr_mask);
|
|
}
|
|
|
|
static u8
|
|
i2c_dw_recv_len(struct dw_i2c_dev *dev, u8 len)
|
|
{
|
|
struct i2c_msg *msgs = dev->msgs;
|
|
u32 flags = msgs[dev->msg_read_idx].flags;
|
|
|
|
/*
|
|
* Adjust the buffer length and mask the flag
|
|
* after receiving the first byte.
|
|
*/
|
|
len += (flags & I2C_CLIENT_PEC) ? 2 : 1;
|
|
dev->tx_buf_len = len - min_t(u8, len, dev->rx_outstanding);
|
|
msgs[dev->msg_read_idx].len = len;
|
|
msgs[dev->msg_read_idx].flags &= ~I2C_M_RECV_LEN;
|
|
|
|
return len;
|
|
}
|
|
|
|
static void
|
|
i2c_dw_read(struct dw_i2c_dev *dev)
|
|
{
|
|
struct i2c_msg *msgs = dev->msgs;
|
|
unsigned int rx_valid;
|
|
|
|
for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
|
|
unsigned int tmp;
|
|
u32 len;
|
|
u8 *buf;
|
|
|
|
if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
|
|
continue;
|
|
|
|
if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
|
|
len = msgs[dev->msg_read_idx].len;
|
|
buf = msgs[dev->msg_read_idx].buf;
|
|
} else {
|
|
len = dev->rx_buf_len;
|
|
buf = dev->rx_buf;
|
|
}
|
|
|
|
regmap_read(dev->map, DW_IC_RXFLR, &rx_valid);
|
|
|
|
for (; len > 0 && rx_valid > 0; len--, rx_valid--) {
|
|
u32 flags = msgs[dev->msg_read_idx].flags;
|
|
|
|
regmap_read(dev->map, DW_IC_DATA_CMD, &tmp);
|
|
tmp &= DW_IC_DATA_CMD_DAT;
|
|
/* Ensure length byte is a valid value */
|
|
if (flags & I2C_M_RECV_LEN) {
|
|
/*
|
|
* if IC_EMPTYFIFO_HOLD_MASTER_EN is set, which cannot be
|
|
* detected from the registers, the controller can be
|
|
* disabled if the STOP bit is set. But it is only set
|
|
* after receiving block data response length in
|
|
* I2C_FUNC_SMBUS_BLOCK_DATA case. That needs to read
|
|
* another byte with STOP bit set when the block data
|
|
* response length is invalid to complete the transaction.
|
|
*/
|
|
if (!tmp || tmp > I2C_SMBUS_BLOCK_MAX)
|
|
tmp = 1;
|
|
|
|
len = i2c_dw_recv_len(dev, tmp);
|
|
}
|
|
*buf++ = tmp;
|
|
dev->rx_outstanding--;
|
|
}
|
|
|
|
if (len > 0) {
|
|
dev->status |= STATUS_READ_IN_PROGRESS;
|
|
dev->rx_buf_len = len;
|
|
dev->rx_buf = buf;
|
|
return;
|
|
} else
|
|
dev->status &= ~STATUS_READ_IN_PROGRESS;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Prepare controller for a transaction and call i2c_dw_xfer_msg.
|
|
*/
|
|
static int
|
|
i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
|
|
{
|
|
struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
|
|
int ret;
|
|
|
|
dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
|
|
|
|
pm_runtime_get_sync(dev->dev);
|
|
|
|
/*
|
|
* Initiate I2C message transfer when polling mode is enabled,
|
|
* As it is polling based transfer mechanism, which does not support
|
|
* interrupt based functionalities of existing DesignWare driver.
|
|
*/
|
|
switch (dev->flags & MODEL_MASK) {
|
|
case MODEL_AMD_NAVI_GPU:
|
|
ret = amd_i2c_dw_xfer_quirk(adap, msgs, num);
|
|
goto done_nolock;
|
|
case MODEL_WANGXUN_SP:
|
|
ret = txgbe_i2c_dw_xfer_quirk(adap, msgs, num);
|
|
goto done_nolock;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
reinit_completion(&dev->cmd_complete);
|
|
dev->msgs = msgs;
|
|
dev->msgs_num = num;
|
|
dev->cmd_err = 0;
|
|
dev->msg_write_idx = 0;
|
|
dev->msg_read_idx = 0;
|
|
dev->msg_err = 0;
|
|
dev->status = 0;
|
|
dev->abort_source = 0;
|
|
dev->rx_outstanding = 0;
|
|
|
|
ret = i2c_dw_acquire_lock(dev);
|
|
if (ret)
|
|
goto done_nolock;
|
|
|
|
ret = i2c_dw_wait_bus_not_busy(dev);
|
|
if (ret < 0)
|
|
goto done;
|
|
|
|
/* Start the transfers */
|
|
i2c_dw_xfer_init(dev);
|
|
|
|
/* Wait for tx to complete */
|
|
if (!wait_for_completion_timeout(&dev->cmd_complete, adap->timeout)) {
|
|
dev_err(dev->dev, "controller timed out\n");
|
|
/* i2c_dw_init implicitly disables the adapter */
|
|
i2c_recover_bus(&dev->adapter);
|
|
i2c_dw_init_master(dev);
|
|
ret = -ETIMEDOUT;
|
|
goto done;
|
|
}
|
|
|
|
/*
|
|
* We must disable the adapter before returning and signaling the end
|
|
* of the current transfer. Otherwise the hardware might continue
|
|
* generating interrupts which in turn causes a race condition with
|
|
* the following transfer. Needs some more investigation if the
|
|
* additional interrupts are a hardware bug or this driver doesn't
|
|
* handle them correctly yet.
|
|
*/
|
|
__i2c_dw_disable_nowait(dev);
|
|
|
|
if (dev->msg_err) {
|
|
ret = dev->msg_err;
|
|
goto done;
|
|
}
|
|
|
|
/* No error */
|
|
if (likely(!dev->cmd_err && !dev->status)) {
|
|
ret = num;
|
|
goto done;
|
|
}
|
|
|
|
/* We have an error */
|
|
if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
|
|
ret = i2c_dw_handle_tx_abort(dev);
|
|
goto done;
|
|
}
|
|
|
|
if (dev->status)
|
|
dev_err(dev->dev,
|
|
"transfer terminated early - interrupt latency too high?\n");
|
|
|
|
ret = -EIO;
|
|
|
|
done:
|
|
i2c_dw_release_lock(dev);
|
|
|
|
done_nolock:
|
|
pm_runtime_mark_last_busy(dev->dev);
|
|
pm_runtime_put_autosuspend(dev->dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct i2c_algorithm i2c_dw_algo = {
|
|
.master_xfer = i2c_dw_xfer,
|
|
.functionality = i2c_dw_func,
|
|
};
|
|
|
|
static const struct i2c_adapter_quirks i2c_dw_quirks = {
|
|
.flags = I2C_AQ_NO_ZERO_LEN,
|
|
};
|
|
|
|
static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
|
|
{
|
|
unsigned int stat, dummy;
|
|
|
|
/*
|
|
* The IC_INTR_STAT register just indicates "enabled" interrupts.
|
|
* The unmasked raw version of interrupt status bits is available
|
|
* in the IC_RAW_INTR_STAT register.
|
|
*
|
|
* That is,
|
|
* stat = readl(IC_INTR_STAT);
|
|
* equals to,
|
|
* stat = readl(IC_RAW_INTR_STAT) & readl(IC_INTR_MASK);
|
|
*
|
|
* The raw version might be useful for debugging purposes.
|
|
*/
|
|
regmap_read(dev->map, DW_IC_INTR_STAT, &stat);
|
|
|
|
/*
|
|
* Do not use the IC_CLR_INTR register to clear interrupts, or
|
|
* you'll miss some interrupts, triggered during the period from
|
|
* readl(IC_INTR_STAT) to readl(IC_CLR_INTR).
|
|
*
|
|
* Instead, use the separately-prepared IC_CLR_* registers.
|
|
*/
|
|
if (stat & DW_IC_INTR_RX_UNDER)
|
|
regmap_read(dev->map, DW_IC_CLR_RX_UNDER, &dummy);
|
|
if (stat & DW_IC_INTR_RX_OVER)
|
|
regmap_read(dev->map, DW_IC_CLR_RX_OVER, &dummy);
|
|
if (stat & DW_IC_INTR_TX_OVER)
|
|
regmap_read(dev->map, DW_IC_CLR_TX_OVER, &dummy);
|
|
if (stat & DW_IC_INTR_RD_REQ)
|
|
regmap_read(dev->map, DW_IC_CLR_RD_REQ, &dummy);
|
|
if (stat & DW_IC_INTR_TX_ABRT) {
|
|
/*
|
|
* The IC_TX_ABRT_SOURCE register is cleared whenever
|
|
* the IC_CLR_TX_ABRT is read. Preserve it beforehand.
|
|
*/
|
|
regmap_read(dev->map, DW_IC_TX_ABRT_SOURCE, &dev->abort_source);
|
|
regmap_read(dev->map, DW_IC_CLR_TX_ABRT, &dummy);
|
|
}
|
|
if (stat & DW_IC_INTR_RX_DONE)
|
|
regmap_read(dev->map, DW_IC_CLR_RX_DONE, &dummy);
|
|
if (stat & DW_IC_INTR_ACTIVITY)
|
|
regmap_read(dev->map, DW_IC_CLR_ACTIVITY, &dummy);
|
|
if ((stat & DW_IC_INTR_STOP_DET) &&
|
|
((dev->rx_outstanding == 0) || (stat & DW_IC_INTR_RX_FULL)))
|
|
regmap_read(dev->map, DW_IC_CLR_STOP_DET, &dummy);
|
|
if (stat & DW_IC_INTR_START_DET)
|
|
regmap_read(dev->map, DW_IC_CLR_START_DET, &dummy);
|
|
if (stat & DW_IC_INTR_GEN_CALL)
|
|
regmap_read(dev->map, DW_IC_CLR_GEN_CALL, &dummy);
|
|
|
|
return stat;
|
|
}
|
|
|
|
/*
|
|
* Interrupt service routine. This gets called whenever an I2C master interrupt
|
|
* occurs.
|
|
*/
|
|
static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
|
|
{
|
|
struct dw_i2c_dev *dev = dev_id;
|
|
unsigned int stat, enabled;
|
|
|
|
regmap_read(dev->map, DW_IC_ENABLE, &enabled);
|
|
regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &stat);
|
|
if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
|
|
return IRQ_NONE;
|
|
if (pm_runtime_suspended(dev->dev) || stat == GENMASK(31, 0))
|
|
return IRQ_NONE;
|
|
dev_dbg(dev->dev, "enabled=%#x stat=%#x\n", enabled, stat);
|
|
|
|
stat = i2c_dw_read_clear_intrbits(dev);
|
|
|
|
if (!(dev->status & STATUS_ACTIVE)) {
|
|
/*
|
|
* Unexpected interrupt in driver point of view. State
|
|
* variables are either unset or stale so acknowledge and
|
|
* disable interrupts for suppressing further interrupts if
|
|
* interrupt really came from this HW (E.g. firmware has left
|
|
* the HW active).
|
|
*/
|
|
regmap_write(dev->map, DW_IC_INTR_MASK, 0);
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
if (stat & DW_IC_INTR_TX_ABRT) {
|
|
dev->cmd_err |= DW_IC_ERR_TX_ABRT;
|
|
dev->status &= ~STATUS_MASK;
|
|
dev->rx_outstanding = 0;
|
|
|
|
/*
|
|
* Anytime TX_ABRT is set, the contents of the tx/rx
|
|
* buffers are flushed. Make sure to skip them.
|
|
*/
|
|
regmap_write(dev->map, DW_IC_INTR_MASK, 0);
|
|
goto tx_aborted;
|
|
}
|
|
|
|
if (stat & DW_IC_INTR_RX_FULL)
|
|
i2c_dw_read(dev);
|
|
|
|
if (stat & DW_IC_INTR_TX_EMPTY)
|
|
i2c_dw_xfer_msg(dev);
|
|
|
|
/*
|
|
* No need to modify or disable the interrupt mask here.
|
|
* i2c_dw_xfer_msg() will take care of it according to
|
|
* the current transmit status.
|
|
*/
|
|
|
|
tx_aborted:
|
|
if (((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err) &&
|
|
(dev->rx_outstanding == 0))
|
|
complete(&dev->cmd_complete);
|
|
else if (unlikely(dev->flags & ACCESS_INTR_MASK)) {
|
|
/* Workaround to trigger pending interrupt */
|
|
regmap_read(dev->map, DW_IC_INTR_MASK, &stat);
|
|
regmap_write(dev->map, DW_IC_INTR_MASK, 0);
|
|
regmap_write(dev->map, DW_IC_INTR_MASK, stat);
|
|
}
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
void i2c_dw_configure_master(struct dw_i2c_dev *dev)
|
|
{
|
|
struct i2c_timings *t = &dev->timings;
|
|
|
|
dev->functionality = I2C_FUNC_10BIT_ADDR | DW_IC_DEFAULT_FUNCTIONALITY;
|
|
|
|
dev->master_cfg = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE |
|
|
DW_IC_CON_RESTART_EN;
|
|
|
|
dev->mode = DW_IC_MASTER;
|
|
|
|
switch (t->bus_freq_hz) {
|
|
case I2C_MAX_STANDARD_MODE_FREQ:
|
|
dev->master_cfg |= DW_IC_CON_SPEED_STD;
|
|
break;
|
|
case I2C_MAX_HIGH_SPEED_MODE_FREQ:
|
|
dev->master_cfg |= DW_IC_CON_SPEED_HIGH;
|
|
break;
|
|
default:
|
|
dev->master_cfg |= DW_IC_CON_SPEED_FAST;
|
|
}
|
|
}
|
|
EXPORT_SYMBOL_GPL(i2c_dw_configure_master);
|
|
|
|
static void i2c_dw_prepare_recovery(struct i2c_adapter *adap)
|
|
{
|
|
struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
|
|
|
|
i2c_dw_disable(dev);
|
|
reset_control_assert(dev->rst);
|
|
i2c_dw_prepare_clk(dev, false);
|
|
}
|
|
|
|
static void i2c_dw_unprepare_recovery(struct i2c_adapter *adap)
|
|
{
|
|
struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
|
|
|
|
i2c_dw_prepare_clk(dev, true);
|
|
reset_control_deassert(dev->rst);
|
|
i2c_dw_init_master(dev);
|
|
}
|
|
|
|
static int i2c_dw_init_recovery_info(struct dw_i2c_dev *dev)
|
|
{
|
|
struct i2c_bus_recovery_info *rinfo = &dev->rinfo;
|
|
struct i2c_adapter *adap = &dev->adapter;
|
|
struct gpio_desc *gpio;
|
|
|
|
gpio = devm_gpiod_get_optional(dev->dev, "scl", GPIOD_OUT_HIGH);
|
|
if (IS_ERR_OR_NULL(gpio))
|
|
return PTR_ERR_OR_ZERO(gpio);
|
|
|
|
rinfo->scl_gpiod = gpio;
|
|
|
|
gpio = devm_gpiod_get_optional(dev->dev, "sda", GPIOD_IN);
|
|
if (IS_ERR(gpio))
|
|
return PTR_ERR(gpio);
|
|
rinfo->sda_gpiod = gpio;
|
|
|
|
rinfo->pinctrl = devm_pinctrl_get(dev->dev);
|
|
if (IS_ERR(rinfo->pinctrl)) {
|
|
if (PTR_ERR(rinfo->pinctrl) == -EPROBE_DEFER)
|
|
return PTR_ERR(rinfo->pinctrl);
|
|
|
|
rinfo->pinctrl = NULL;
|
|
dev_err(dev->dev, "getting pinctrl info failed: bus recovery might not work\n");
|
|
} else if (!rinfo->pinctrl) {
|
|
dev_dbg(dev->dev, "pinctrl is disabled, bus recovery might not work\n");
|
|
}
|
|
|
|
rinfo->recover_bus = i2c_generic_scl_recovery;
|
|
rinfo->prepare_recovery = i2c_dw_prepare_recovery;
|
|
rinfo->unprepare_recovery = i2c_dw_unprepare_recovery;
|
|
adap->bus_recovery_info = rinfo;
|
|
|
|
dev_info(dev->dev, "running with gpio recovery mode! scl%s",
|
|
rinfo->sda_gpiod ? ",sda" : "");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int i2c_dw_poll_adap_quirk(struct dw_i2c_dev *dev)
|
|
{
|
|
struct i2c_adapter *adap = &dev->adapter;
|
|
int ret;
|
|
|
|
pm_runtime_get_noresume(dev->dev);
|
|
ret = i2c_add_numbered_adapter(adap);
|
|
if (ret)
|
|
dev_err(dev->dev, "Failed to add adapter: %d\n", ret);
|
|
pm_runtime_put_noidle(dev->dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static bool i2c_dw_is_model_poll(struct dw_i2c_dev *dev)
|
|
{
|
|
switch (dev->flags & MODEL_MASK) {
|
|
case MODEL_AMD_NAVI_GPU:
|
|
case MODEL_WANGXUN_SP:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
int i2c_dw_probe_master(struct dw_i2c_dev *dev)
|
|
{
|
|
struct i2c_adapter *adap = &dev->adapter;
|
|
unsigned long irq_flags;
|
|
unsigned int ic_con;
|
|
int ret;
|
|
|
|
init_completion(&dev->cmd_complete);
|
|
|
|
dev->init = i2c_dw_init_master;
|
|
dev->disable = i2c_dw_disable;
|
|
|
|
ret = i2c_dw_init_regmap(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = i2c_dw_set_timings_master(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = i2c_dw_set_fifo_size(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Lock the bus for accessing DW_IC_CON */
|
|
ret = i2c_dw_acquire_lock(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/*
|
|
* On AMD platforms BIOS advertises the bus clear feature
|
|
* and enables the SCL/SDA stuck low. SMU FW does the
|
|
* bus recovery process. Driver should not ignore this BIOS
|
|
* advertisement of bus clear feature.
|
|
*/
|
|
ret = regmap_read(dev->map, DW_IC_CON, &ic_con);
|
|
i2c_dw_release_lock(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (ic_con & DW_IC_CON_BUS_CLEAR_CTRL)
|
|
dev->master_cfg |= DW_IC_CON_BUS_CLEAR_CTRL;
|
|
|
|
ret = dev->init(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
snprintf(adap->name, sizeof(adap->name),
|
|
"Synopsys DesignWare I2C adapter");
|
|
adap->retries = 3;
|
|
adap->algo = &i2c_dw_algo;
|
|
adap->quirks = &i2c_dw_quirks;
|
|
adap->dev.parent = dev->dev;
|
|
i2c_set_adapdata(adap, dev);
|
|
|
|
if (i2c_dw_is_model_poll(dev))
|
|
return i2c_dw_poll_adap_quirk(dev);
|
|
|
|
if (dev->flags & ACCESS_NO_IRQ_SUSPEND) {
|
|
irq_flags = IRQF_NO_SUSPEND;
|
|
} else {
|
|
irq_flags = IRQF_SHARED | IRQF_COND_SUSPEND;
|
|
}
|
|
|
|
ret = i2c_dw_acquire_lock(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
regmap_write(dev->map, DW_IC_INTR_MASK, 0);
|
|
i2c_dw_release_lock(dev);
|
|
|
|
ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr, irq_flags,
|
|
dev_name(dev->dev), dev);
|
|
if (ret) {
|
|
dev_err(dev->dev, "failure requesting irq %i: %d\n",
|
|
dev->irq, ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = i2c_dw_init_recovery_info(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/*
|
|
* Increment PM usage count during adapter registration in order to
|
|
* avoid possible spurious runtime suspend when adapter device is
|
|
* registered to the device core and immediate resume in case bus has
|
|
* registered I2C slaves that do I2C transfers in their probe.
|
|
*/
|
|
pm_runtime_get_noresume(dev->dev);
|
|
ret = i2c_add_numbered_adapter(adap);
|
|
if (ret)
|
|
dev_err(dev->dev, "failure adding adapter: %d\n", ret);
|
|
pm_runtime_put_noidle(dev->dev);
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(i2c_dw_probe_master);
|
|
|
|
MODULE_DESCRIPTION("Synopsys DesignWare I2C bus master adapter");
|
|
MODULE_LICENSE("GPL");
|