mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-17 16:14:25 +08:00
81279f5d08
Add driver for the StarFive JH7110 Image-Signal-Process clock controller. And these clock controllers should power on and enable the clocks from SYSCRG before registering. Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
18 lines
406 B
C
18 lines
406 B
C
/* SPDX-License-Identifier: GPL-2.0 */
|
|
#ifndef __CLK_STARFIVE_JH7110_H
|
|
#define __CLK_STARFIVE_JH7110_H
|
|
|
|
#include "clk-starfive-jh71x0.h"
|
|
|
|
/* top clocks of ISP/VOUT domain from JH7110 SYSCRG */
|
|
struct jh7110_top_sysclk {
|
|
struct clk_bulk_data *top_clks;
|
|
int top_clks_num;
|
|
};
|
|
|
|
int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv,
|
|
const char *adev_name,
|
|
u32 adev_id);
|
|
|
|
#endif
|