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Add crypto_engine support for RSA algorithms, to make use of the engine queue. The requests, with backlog flag, will be listed into crypto-engine queue and processed by CAAM when free. In case the queue is empty, the request is directly sent to CAAM. Only the backlog request are sent to crypto-engine since the others can be handled by CAAM, if free, especially since JR has up to 1024 entries (more than the 10 entries from crypto-engine). Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
159 lines
5.1 KiB
C
159 lines
5.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* caam - Freescale FSL CAAM support for Public Key Cryptography descriptors
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*
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* Copyright 2016 Freescale Semiconductor, Inc.
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*
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* There is no Shared Descriptor for PKC so that the Job Descriptor must carry
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* all the desired key parameters, input and output pointers.
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*/
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#ifndef _PKC_DESC_H_
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#define _PKC_DESC_H_
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#include "compat.h"
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#include "pdb.h"
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#include <crypto/engine.h>
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/**
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* caam_priv_key_form - CAAM RSA private key representation
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* CAAM RSA private key may have either of three forms.
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*
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* 1. The first representation consists of the pair (n, d), where the
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* components have the following meanings:
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* n the RSA modulus
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* d the RSA private exponent
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*
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* 2. The second representation consists of the triplet (p, q, d), where the
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* components have the following meanings:
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* p the first prime factor of the RSA modulus n
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* q the second prime factor of the RSA modulus n
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* d the RSA private exponent
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*
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* 3. The third representation consists of the quintuple (p, q, dP, dQ, qInv),
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* where the components have the following meanings:
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* p the first prime factor of the RSA modulus n
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* q the second prime factor of the RSA modulus n
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* dP the first factors's CRT exponent
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* dQ the second factors's CRT exponent
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* qInv the (first) CRT coefficient
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*
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* The benefit of using the third or the second key form is lower computational
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* cost for the decryption and signature operations.
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*/
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enum caam_priv_key_form {
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FORM1,
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FORM2,
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FORM3
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};
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/**
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* caam_rsa_key - CAAM RSA key structure. Keys are allocated in DMA zone.
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* @n : RSA modulus raw byte stream
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* @e : RSA public exponent raw byte stream
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* @d : RSA private exponent raw byte stream
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* @p : RSA prime factor p of RSA modulus n
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* @q : RSA prime factor q of RSA modulus n
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* @dp : RSA CRT exponent of p
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* @dp : RSA CRT exponent of q
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* @qinv : RSA CRT coefficient
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* @tmp1 : CAAM uses this temporary buffer as internal state buffer.
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* It is assumed to be as long as p.
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* @tmp2 : CAAM uses this temporary buffer as internal state buffer.
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* It is assumed to be as long as q.
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* @n_sz : length in bytes of RSA modulus n
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* @e_sz : length in bytes of RSA public exponent
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* @d_sz : length in bytes of RSA private exponent
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* @p_sz : length in bytes of RSA prime factor p of RSA modulus n
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* @q_sz : length in bytes of RSA prime factor q of RSA modulus n
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* @priv_form : CAAM RSA private key representation
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*/
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struct caam_rsa_key {
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u8 *n;
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u8 *e;
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u8 *d;
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u8 *p;
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u8 *q;
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u8 *dp;
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u8 *dq;
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u8 *qinv;
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u8 *tmp1;
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u8 *tmp2;
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size_t n_sz;
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size_t e_sz;
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size_t d_sz;
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size_t p_sz;
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size_t q_sz;
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enum caam_priv_key_form priv_form;
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};
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/**
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* caam_rsa_ctx - per session context.
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* @enginectx : crypto engine context
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* @key : RSA key in DMA zone
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* @dev : device structure
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* @padding_dma : dma address of padding, for adding it to the input
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*/
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struct caam_rsa_ctx {
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struct crypto_engine_ctx enginectx;
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struct caam_rsa_key key;
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struct device *dev;
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dma_addr_t padding_dma;
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};
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/**
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* caam_rsa_req_ctx - per request context.
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* @src : input scatterlist (stripped of leading zeros)
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* @fixup_src : input scatterlist (that might be stripped of leading zeros)
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* @fixup_src_len : length of the fixup_src input scatterlist
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* @edesc : s/w-extended rsa descriptor
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* @akcipher_op_done : callback used when operation is done
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*/
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struct caam_rsa_req_ctx {
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struct scatterlist src[2];
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struct scatterlist *fixup_src;
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unsigned int fixup_src_len;
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struct rsa_edesc *edesc;
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void (*akcipher_op_done)(struct device *jrdev, u32 *desc, u32 err,
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void *context);
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};
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/**
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* rsa_edesc - s/w-extended rsa descriptor
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* @src_nents : number of segments in input s/w scatterlist
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* @dst_nents : number of segments in output s/w scatterlist
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* @mapped_src_nents: number of segments in input h/w link table
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* @mapped_dst_nents: number of segments in output h/w link table
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* @sec4_sg_bytes : length of h/w link table
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* @bklog : stored to determine if the request needs backlog
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* @sec4_sg_dma : dma address of h/w link table
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* @sec4_sg : pointer to h/w link table
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* @pdb : specific RSA Protocol Data Block (PDB)
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* @hw_desc : descriptor followed by link tables if any
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*/
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struct rsa_edesc {
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int src_nents;
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int dst_nents;
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int mapped_src_nents;
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int mapped_dst_nents;
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int sec4_sg_bytes;
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bool bklog;
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dma_addr_t sec4_sg_dma;
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struct sec4_sg_entry *sec4_sg;
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union {
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struct rsa_pub_pdb pub;
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struct rsa_priv_f1_pdb priv_f1;
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struct rsa_priv_f2_pdb priv_f2;
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struct rsa_priv_f3_pdb priv_f3;
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} pdb;
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u32 hw_desc[];
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};
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/* Descriptor construction primitives. */
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void init_rsa_pub_desc(u32 *desc, struct rsa_pub_pdb *pdb);
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void init_rsa_priv_f1_desc(u32 *desc, struct rsa_priv_f1_pdb *pdb);
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void init_rsa_priv_f2_desc(u32 *desc, struct rsa_priv_f2_pdb *pdb);
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void init_rsa_priv_f3_desc(u32 *desc, struct rsa_priv_f3_pdb *pdb);
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#endif
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