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The Marvell Armada 375 and Armada 38x SOCs, which use the Cortex-A9 CPU core, the PL310 cache and the Marvell PCIe hardware block are affected a L2/PCIe deadlock caused by a system erratum when hardware I/O coherency is used. This deadlock can be avoided by mapping the PCIe memory areas as strongly-ordered (note: MT_UNCACHED is strongly-ordered), and by removing the outer cache sync done in software. This is implemented in this patch by: * Registering a custom arch_ioremap_caller function that allows to make sure PCI memory regions are mapped MT_UNCACHED. * Adding at runtime the 'arm,io-coherent' property to the PL310 cache controller. This cannot be done permanently in the DT, because the hardware I/O coherency can only be enabled when CONFIG_SMP is enabled, in the current kernel situation. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1400165974-9059-4-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net> |
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| .. | ||
| include/mach | ||
| armada-370-xp.h | ||
| board-v7.c | ||
| board.h | ||
| coherency_ll.S | ||
| coherency.c | ||
| coherency.h | ||
| common.h | ||
| cpu-reset.c | ||
| dove.c | ||
| headsmp-a9.S | ||
| headsmp.S | ||
| hotplug.c | ||
| Kconfig | ||
| kirkwood-pm.c | ||
| kirkwood-pm.h | ||
| kirkwood.c | ||
| kirkwood.h | ||
| Makefile | ||
| mvebu-soc-id.c | ||
| mvebu-soc-id.h | ||
| platsmp-a9.c | ||
| platsmp.c | ||
| pmsu.c | ||
| pmsu.h | ||
| system-controller.c | ||