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f8f2a8522a
Fix a hole in the VFP thread migration. Lets define two threads.
Thread 1, we'll call 'interesting_thread' which is a thread which is
running on CPU0, using VFP (so vfp_current_hw_state[0] =
&interesting_thread->vfpstate) and gets migrated off to CPU1, where
it continues execution of VFP instructions.
Thread 2, we'll call 'new_cpu0_thread' which is the thread which takes
over on CPU0. This has also been using VFP, and last used VFP on CPU0,
but doesn't use it again.
The following code will be executed twice:
cpu = thread->cpu;
/*
* On SMP, if VFP is enabled, save the old state in
* case the thread migrates to a different CPU. The
* restoring is done lazily.
*/
if ((fpexc & FPEXC_EN) && vfp_current_hw_state[cpu]) {
vfp_save_state(vfp_current_hw_state[cpu], fpexc);
vfp_current_hw_state[cpu]->hard.cpu = cpu;
}
/*
* Thread migration, just force the reloading of the
* state on the new CPU in case the VFP registers
* contain stale data.
*/
if (thread->vfpstate.hard.cpu != cpu)
vfp_current_hw_state[cpu] = NULL;
The first execution will be on CPU0 to switch away from 'interesting_thread'.
interesting_thread->cpu will be 0.
So, vfp_current_hw_state[0] points at interesting_thread->vfpstate.
The hardware state will be saved, along with the CPU number (0) that
it was executing on.
'thread' will be 'new_cpu0_thread' with new_cpu0_thread->cpu = 0.
Also, because it was executing on CPU0, new_cpu0_thread->vfpstate.hard.cpu = 0,
and so the thread migration check is not triggered.
This means that vfp_current_hw_state[0] remains pointing at interesting_thread.
The second execution will be on CPU1 to switch _to_ 'interesting_thread'.
So, 'thread' will be 'interesting_thread' and interesting_thread->cpu now
will be 1. The previous thread executing on CPU1 is not relevant to this
so we shall ignore that.
We get to the thread migration check. Here, we discover that
interesting_thread->vfpstate.hard.cpu = 0, yet interesting_thread->cpu is
now 1, indicating thread migration. We set vfp_current_hw_state[1] to
NULL.
So, at this point vfp_current_hw_state[] contains the following:
[0] = &interesting_thread->vfpstate
[1] = NULL
Our interesting thread now executes a VFP instruction, takes a fault
which loads the state into the VFP hardware. Now, through the assembly
we now have:
[0] = &interesting_thread->vfpstate
[1] = &interesting_thread->vfpstate
CPU1 stops due to ptrace (and so saves its VFP state) using the thread
switch code above), and CPU0 calls vfp_sync_hwstate().
if (vfp_current_hw_state[cpu] == &thread->vfpstate) {
vfp_save_state(&thread->vfpstate, fpexc | FPEXC_EN);
BANG, we corrupt interesting_thread's VFP state by overwriting the
more up-to-date state saved by CPU1 with the old VFP state from CPU0.
Fix this by ensuring that we have sane semantics for the various state
describing variables:
1. vfp_current_hw_state[] points to the current owner of the context
information stored in each CPUs hardware, or NULL if that state
information is invalid.
2. thread->vfpstate.hard.cpu always contains the most recent CPU number
which the state was loaded into or NR_CPUS if no CPU owns the state.
So, for a particular CPU to be a valid owner of the VFP state for a
particular thread t, two things must be true:
vfp_current_hw_state[cpu] == &t->vfpstate && t->vfpstate.hard.cpu == cpu.
and that is valid from the moment a CPU loads the saved VFP context
into the hardware. This gives clear and consistent semantics to
interpreting these variables.
This patch also fixes thread copying, ensuring that t->vfpstate.hard.cpu
is invalidated, otherwise CPU0 may believe it was the last owner. The
hole can happen thus:
- thread1 runs on CPU2 using VFP, migrates to CPU3, exits and thread_info
freed.
- New thread allocated from a previously running thread on CPU2, reusing
memory for thread1 and copying vfp.hard.cpu.
At this point, the following are true:
new_thread1->vfpstate.hard.cpu == 2
&new_thread1->vfpstate == vfp_current_hw_state[2]
Lastly, this also addresses thread flushing in a similar way to thread
copying. Hole is:
- thread runs on CPU0, using VFP, migrates to CPU1 but does not use VFP.
- thread calls execve(), so thread flush happens, leaving
vfp_current_hw_state[0] intact. This vfpstate is memset to 0 causing
thread->vfpstate.hard.cpu = 0.
- thread migrates back to CPU0 before using VFP.
At this point, the following are true:
thread->vfpstate.hard.cpu == 0
&thread->vfpstate == vfp_current_hw_state[0]
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
310 lines
8.2 KiB
ArmAsm
310 lines
8.2 KiB
ArmAsm
/*
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* linux/arch/arm/vfp/vfphw.S
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*
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* Copyright (C) 2004 ARM Limited.
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* Written by Deep Blue Solutions Limited.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This code is called from the kernel's undefined instruction trap.
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* r9 holds the return address for successful handling.
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* lr holds the return address for unrecognised instructions.
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* r10 points at the start of the private FP workspace in the thread structure
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* sp points to a struct pt_regs (as defined in include/asm/proc/ptrace.h)
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*/
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#include <asm/thread_info.h>
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#include <asm/vfpmacros.h>
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#include "../kernel/entry-header.S"
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.macro DBGSTR, str
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#ifdef DEBUG
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stmfd sp!, {r0-r3, ip, lr}
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add r0, pc, #4
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bl printk
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b 1f
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.asciz "<7>VFP: \str\n"
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.balign 4
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1: ldmfd sp!, {r0-r3, ip, lr}
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#endif
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.endm
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.macro DBGSTR1, str, arg
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#ifdef DEBUG
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stmfd sp!, {r0-r3, ip, lr}
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mov r1, \arg
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add r0, pc, #4
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bl printk
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b 1f
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.asciz "<7>VFP: \str\n"
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.balign 4
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1: ldmfd sp!, {r0-r3, ip, lr}
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#endif
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.endm
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.macro DBGSTR3, str, arg1, arg2, arg3
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#ifdef DEBUG
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stmfd sp!, {r0-r3, ip, lr}
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mov r3, \arg3
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mov r2, \arg2
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mov r1, \arg1
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add r0, pc, #4
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bl printk
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b 1f
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.asciz "<7>VFP: \str\n"
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.balign 4
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1: ldmfd sp!, {r0-r3, ip, lr}
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#endif
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.endm
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@ VFP hardware support entry point.
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@
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@ r0 = faulted instruction
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@ r2 = faulted PC+4
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@ r9 = successful return
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@ r10 = vfp_state union
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@ r11 = CPU number
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@ lr = failure return
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ENTRY(vfp_support_entry)
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DBGSTR3 "instr %08x pc %08x state %p", r0, r2, r10
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VFPFMRX r1, FPEXC @ Is the VFP enabled?
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DBGSTR1 "fpexc %08x", r1
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tst r1, #FPEXC_EN
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bne look_for_VFP_exceptions @ VFP is already enabled
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DBGSTR1 "enable %x", r10
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ldr r3, vfp_current_hw_state_address
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orr r1, r1, #FPEXC_EN @ user FPEXC has the enable bit set
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ldr r4, [r3, r11, lsl #2] @ vfp_current_hw_state pointer
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bic r5, r1, #FPEXC_EX @ make sure exceptions are disabled
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cmp r4, r10 @ this thread owns the hw context?
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#ifndef CONFIG_SMP
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@ For UP, checking that this thread owns the hw context is
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@ sufficient to determine that the hardware state is valid.
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beq vfp_hw_state_valid
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@ On UP, we lazily save the VFP context. As a different
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@ thread wants ownership of the VFP hardware, save the old
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@ state if there was a previous (valid) owner.
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VFPFMXR FPEXC, r5 @ enable VFP, disable any pending
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@ exceptions, so we can get at the
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@ rest of it
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DBGSTR1 "save old state %p", r4
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cmp r4, #0 @ if the vfp_current_hw_state is NULL
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beq vfp_reload_hw @ then the hw state needs reloading
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VFPFSTMIA r4, r5 @ save the working registers
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VFPFMRX r5, FPSCR @ current status
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#ifndef CONFIG_CPU_FEROCEON
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tst r1, #FPEXC_EX @ is there additional state to save?
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beq 1f
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VFPFMRX r6, FPINST @ FPINST (only if FPEXC.EX is set)
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tst r1, #FPEXC_FP2V @ is there an FPINST2 to read?
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beq 1f
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VFPFMRX r8, FPINST2 @ FPINST2 if needed (and present)
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1:
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#endif
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stmia r4, {r1, r5, r6, r8} @ save FPEXC, FPSCR, FPINST, FPINST2
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vfp_reload_hw:
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#else
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@ For SMP, if this thread does not own the hw context, then we
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@ need to reload it. No need to save the old state as on SMP,
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@ we always save the state when we switch away from a thread.
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bne vfp_reload_hw
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@ This thread has ownership of the current hardware context.
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@ However, it may have been migrated to another CPU, in which
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@ case the saved state is newer than the hardware context.
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@ Check this by looking at the CPU number which the state was
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@ last loaded onto.
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ldr ip, [r10, #VFP_CPU]
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teq ip, r11
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beq vfp_hw_state_valid
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vfp_reload_hw:
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@ We're loading this threads state into the VFP hardware. Update
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@ the CPU number which contains the most up to date VFP context.
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str r11, [r10, #VFP_CPU]
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VFPFMXR FPEXC, r5 @ enable VFP, disable any pending
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@ exceptions, so we can get at the
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@ rest of it
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#endif
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DBGSTR1 "load state %p", r10
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str r10, [r3, r11, lsl #2] @ update the vfp_current_hw_state pointer
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@ Load the saved state back into the VFP
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VFPFLDMIA r10, r5 @ reload the working registers while
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@ FPEXC is in a safe state
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ldmia r10, {r1, r5, r6, r8} @ load FPEXC, FPSCR, FPINST, FPINST2
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#ifndef CONFIG_CPU_FEROCEON
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tst r1, #FPEXC_EX @ is there additional state to restore?
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beq 1f
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VFPFMXR FPINST, r6 @ restore FPINST (only if FPEXC.EX is set)
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tst r1, #FPEXC_FP2V @ is there an FPINST2 to write?
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beq 1f
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VFPFMXR FPINST2, r8 @ FPINST2 if needed (and present)
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1:
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#endif
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VFPFMXR FPSCR, r5 @ restore status
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@ The context stored in the VFP hardware is up to date with this thread
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vfp_hw_state_valid:
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tst r1, #FPEXC_EX
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bne process_exception @ might as well handle the pending
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@ exception before retrying branch
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@ out before setting an FPEXC that
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@ stops us reading stuff
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VFPFMXR FPEXC, r1 @ restore FPEXC last
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sub r2, r2, #4
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str r2, [sp, #S_PC] @ retry the instruction
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#ifdef CONFIG_PREEMPT
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get_thread_info r10
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ldr r4, [r10, #TI_PREEMPT] @ get preempt count
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sub r11, r4, #1 @ decrement it
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str r11, [r10, #TI_PREEMPT]
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#endif
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mov pc, r9 @ we think we have handled things
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look_for_VFP_exceptions:
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@ Check for synchronous or asynchronous exception
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tst r1, #FPEXC_EX | FPEXC_DEX
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bne process_exception
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@ On some implementations of the VFP subarch 1, setting FPSCR.IXE
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@ causes all the CDP instructions to be bounced synchronously without
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@ setting the FPEXC.EX bit
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VFPFMRX r5, FPSCR
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tst r5, #FPSCR_IXE
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bne process_exception
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@ Fall into hand on to next handler - appropriate coproc instr
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@ not recognised by VFP
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DBGSTR "not VFP"
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#ifdef CONFIG_PREEMPT
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get_thread_info r10
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ldr r4, [r10, #TI_PREEMPT] @ get preempt count
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sub r11, r4, #1 @ decrement it
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str r11, [r10, #TI_PREEMPT]
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#endif
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mov pc, lr
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process_exception:
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DBGSTR "bounce"
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mov r2, sp @ nothing stacked - regdump is at TOS
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mov lr, r9 @ setup for a return to the user code.
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@ Now call the C code to package up the bounce to the support code
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@ r0 holds the trigger instruction
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@ r1 holds the FPEXC value
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@ r2 pointer to register dump
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b VFP_bounce @ we have handled this - the support
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@ code will raise an exception if
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@ required. If not, the user code will
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@ retry the faulted instruction
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ENDPROC(vfp_support_entry)
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ENTRY(vfp_save_state)
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@ Save the current VFP state
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@ r0 - save location
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@ r1 - FPEXC
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DBGSTR1 "save VFP state %p", r0
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VFPFSTMIA r0, r2 @ save the working registers
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VFPFMRX r2, FPSCR @ current status
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tst r1, #FPEXC_EX @ is there additional state to save?
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beq 1f
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VFPFMRX r3, FPINST @ FPINST (only if FPEXC.EX is set)
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tst r1, #FPEXC_FP2V @ is there an FPINST2 to read?
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beq 1f
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VFPFMRX r12, FPINST2 @ FPINST2 if needed (and present)
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1:
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stmia r0, {r1, r2, r3, r12} @ save FPEXC, FPSCR, FPINST, FPINST2
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mov pc, lr
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ENDPROC(vfp_save_state)
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.align
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vfp_current_hw_state_address:
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.word vfp_current_hw_state
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.macro tbl_branch, base, tmp, shift
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#ifdef CONFIG_THUMB2_KERNEL
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adr \tmp, 1f
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add \tmp, \tmp, \base, lsl \shift
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mov pc, \tmp
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#else
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add pc, pc, \base, lsl \shift
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mov r0, r0
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#endif
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1:
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.endm
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ENTRY(vfp_get_float)
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tbl_branch r0, r3, #3
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.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
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1: mrc p10, 0, r0, c\dr, c0, 0 @ fmrs r0, s0
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mov pc, lr
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.org 1b + 8
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1: mrc p10, 0, r0, c\dr, c0, 4 @ fmrs r0, s1
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mov pc, lr
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.org 1b + 8
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.endr
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ENDPROC(vfp_get_float)
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ENTRY(vfp_put_float)
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tbl_branch r1, r3, #3
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.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
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1: mcr p10, 0, r0, c\dr, c0, 0 @ fmsr r0, s0
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mov pc, lr
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.org 1b + 8
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1: mcr p10, 0, r0, c\dr, c0, 4 @ fmsr r0, s1
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mov pc, lr
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.org 1b + 8
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.endr
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ENDPROC(vfp_put_float)
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ENTRY(vfp_get_double)
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tbl_branch r0, r3, #3
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.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
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1: fmrrd r0, r1, d\dr
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mov pc, lr
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.org 1b + 8
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.endr
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#ifdef CONFIG_VFPv3
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@ d16 - d31 registers
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.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
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1: mrrc p11, 3, r0, r1, c\dr @ fmrrd r0, r1, d\dr
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mov pc, lr
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.org 1b + 8
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.endr
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#endif
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@ virtual register 16 (or 32 if VFPv3) for compare with zero
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mov r0, #0
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mov r1, #0
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mov pc, lr
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ENDPROC(vfp_get_double)
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ENTRY(vfp_put_double)
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tbl_branch r2, r3, #3
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.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
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1: fmdrr d\dr, r0, r1
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mov pc, lr
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.org 1b + 8
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.endr
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#ifdef CONFIG_VFPv3
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@ d16 - d31 registers
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.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
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1: mcrr p11, 3, r0, r1, c\dr @ fmdrr r0, r1, d\dr
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mov pc, lr
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.org 1b + 8
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.endr
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#endif
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ENDPROC(vfp_put_double)
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