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763dedfcda
This should be fixed by commit 4c02cba18c
("pinctrl: bcm2835: Fix initial value for direction_output")
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Martin Sperl <kernel@martin.sperl.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
847 lines
23 KiB
C
847 lines
23 KiB
C
/*
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* Driver for Broadcom BCM2835 SPI Controllers
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*
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* Copyright (C) 2012 Chris Boot
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* Copyright (C) 2013 Stephen Warren
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* Copyright (C) 2015 Martin Sperl
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*
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* This driver is inspired by:
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* spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
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* spi-atmel.c, Copyright (C) 2006 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <asm/page.h>
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/of_gpio.h>
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#include <linux/of_irq.h>
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#include <linux/spi/spi.h>
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/* SPI register offsets */
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#define BCM2835_SPI_CS 0x00
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#define BCM2835_SPI_FIFO 0x04
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#define BCM2835_SPI_CLK 0x08
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#define BCM2835_SPI_DLEN 0x0c
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#define BCM2835_SPI_LTOH 0x10
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#define BCM2835_SPI_DC 0x14
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/* Bitfields in CS */
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#define BCM2835_SPI_CS_LEN_LONG 0x02000000
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#define BCM2835_SPI_CS_DMA_LEN 0x01000000
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#define BCM2835_SPI_CS_CSPOL2 0x00800000
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#define BCM2835_SPI_CS_CSPOL1 0x00400000
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#define BCM2835_SPI_CS_CSPOL0 0x00200000
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#define BCM2835_SPI_CS_RXF 0x00100000
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#define BCM2835_SPI_CS_RXR 0x00080000
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#define BCM2835_SPI_CS_TXD 0x00040000
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#define BCM2835_SPI_CS_RXD 0x00020000
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#define BCM2835_SPI_CS_DONE 0x00010000
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#define BCM2835_SPI_CS_LEN 0x00002000
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#define BCM2835_SPI_CS_REN 0x00001000
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#define BCM2835_SPI_CS_ADCS 0x00000800
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#define BCM2835_SPI_CS_INTR 0x00000400
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#define BCM2835_SPI_CS_INTD 0x00000200
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#define BCM2835_SPI_CS_DMAEN 0x00000100
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#define BCM2835_SPI_CS_TA 0x00000080
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#define BCM2835_SPI_CS_CSPOL 0x00000040
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#define BCM2835_SPI_CS_CLEAR_RX 0x00000020
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#define BCM2835_SPI_CS_CLEAR_TX 0x00000010
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#define BCM2835_SPI_CS_CPOL 0x00000008
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#define BCM2835_SPI_CS_CPHA 0x00000004
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#define BCM2835_SPI_CS_CS_10 0x00000002
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#define BCM2835_SPI_CS_CS_01 0x00000001
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#define BCM2835_SPI_POLLING_LIMIT_US 30
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#define BCM2835_SPI_POLLING_JIFFIES 2
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#define BCM2835_SPI_DMA_MIN_LENGTH 96
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#define BCM2835_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
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| SPI_NO_CS | SPI_3WIRE)
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#define DRV_NAME "spi-bcm2835"
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struct bcm2835_spi {
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void __iomem *regs;
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struct clk *clk;
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int irq;
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const u8 *tx_buf;
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u8 *rx_buf;
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int tx_len;
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int rx_len;
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bool dma_pending;
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};
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static inline u32 bcm2835_rd(struct bcm2835_spi *bs, unsigned reg)
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{
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return readl(bs->regs + reg);
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}
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static inline void bcm2835_wr(struct bcm2835_spi *bs, unsigned reg, u32 val)
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{
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writel(val, bs->regs + reg);
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}
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static inline void bcm2835_rd_fifo(struct bcm2835_spi *bs)
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{
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u8 byte;
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while ((bs->rx_len) &&
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(bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_RXD)) {
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byte = bcm2835_rd(bs, BCM2835_SPI_FIFO);
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if (bs->rx_buf)
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*bs->rx_buf++ = byte;
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bs->rx_len--;
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}
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}
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static inline void bcm2835_wr_fifo(struct bcm2835_spi *bs)
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{
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u8 byte;
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while ((bs->tx_len) &&
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(bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_TXD)) {
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byte = bs->tx_buf ? *bs->tx_buf++ : 0;
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bcm2835_wr(bs, BCM2835_SPI_FIFO, byte);
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bs->tx_len--;
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}
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}
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static void bcm2835_spi_reset_hw(struct spi_master *master)
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{
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struct bcm2835_spi *bs = spi_master_get_devdata(master);
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u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
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/* Disable SPI interrupts and transfer */
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cs &= ~(BCM2835_SPI_CS_INTR |
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BCM2835_SPI_CS_INTD |
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BCM2835_SPI_CS_DMAEN |
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BCM2835_SPI_CS_TA);
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/* and reset RX/TX FIFOS */
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cs |= BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX;
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/* and reset the SPI_HW */
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bcm2835_wr(bs, BCM2835_SPI_CS, cs);
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/* as well as DLEN */
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bcm2835_wr(bs, BCM2835_SPI_DLEN, 0);
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}
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static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id)
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{
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struct spi_master *master = dev_id;
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struct bcm2835_spi *bs = spi_master_get_devdata(master);
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/* Read as many bytes as possible from FIFO */
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bcm2835_rd_fifo(bs);
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/* Write as many bytes as possible to FIFO */
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bcm2835_wr_fifo(bs);
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/* based on flags decide if we can finish the transfer */
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if (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_DONE) {
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/* Transfer complete - reset SPI HW */
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bcm2835_spi_reset_hw(master);
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/* wake up the framework */
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complete(&master->xfer_completion);
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}
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return IRQ_HANDLED;
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}
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static int bcm2835_spi_transfer_one_irq(struct spi_master *master,
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struct spi_device *spi,
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struct spi_transfer *tfr,
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u32 cs)
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{
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struct bcm2835_spi *bs = spi_master_get_devdata(master);
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/* fill in fifo if we have gpio-cs
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* note that there have been rare events where the native-CS
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* flapped for <1us which may change the behaviour
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* with gpio-cs this does not happen, so it is implemented
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* only for this case
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*/
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if (gpio_is_valid(spi->cs_gpio)) {
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/* enable HW block, but without interrupts enabled
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* this would triggern an immediate interrupt
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*/
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bcm2835_wr(bs, BCM2835_SPI_CS,
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cs | BCM2835_SPI_CS_TA);
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/* fill in tx fifo as much as possible */
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bcm2835_wr_fifo(bs);
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}
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/*
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* Enable the HW block. This will immediately trigger a DONE (TX
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* empty) interrupt, upon which we will fill the TX FIFO with the
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* first TX bytes. Pre-filling the TX FIFO here to avoid the
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* interrupt doesn't work:-(
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*/
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cs |= BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD | BCM2835_SPI_CS_TA;
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bcm2835_wr(bs, BCM2835_SPI_CS, cs);
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/* signal that we need to wait for completion */
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return 1;
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}
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/*
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* DMA support
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*
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* this implementation has currently a few issues in so far as it does
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* not work arrount limitations of the HW.
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*
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* the main one being that DMA transfers are limited to 16 bit
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* (so 0 to 65535 bytes) by the SPI HW due to BCM2835_SPI_DLEN
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*
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* also we currently assume that the scatter-gather fragments are
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* all multiple of 4 (except the last) - otherwise we would need
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* to reset the FIFO before subsequent transfers...
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* this also means that tx/rx transfers sg's need to be of equal size!
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*
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* there may be a few more border-cases we may need to address as well
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* but unfortunately this would mean splitting up the scatter-gather
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* list making it slightly unpractical...
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*/
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static void bcm2835_spi_dma_done(void *data)
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{
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struct spi_master *master = data;
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struct bcm2835_spi *bs = spi_master_get_devdata(master);
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/* reset fifo and HW */
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bcm2835_spi_reset_hw(master);
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/* and terminate tx-dma as we do not have an irq for it
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* because when the rx dma will terminate and this callback
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* is called the tx-dma must have finished - can't get to this
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* situation otherwise...
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*/
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dmaengine_terminate_all(master->dma_tx);
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/* mark as no longer pending */
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bs->dma_pending = 0;
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/* and mark as completed */;
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complete(&master->xfer_completion);
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}
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static int bcm2835_spi_prepare_sg(struct spi_master *master,
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struct spi_transfer *tfr,
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bool is_tx)
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{
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struct dma_chan *chan;
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struct scatterlist *sgl;
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unsigned int nents;
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enum dma_transfer_direction dir;
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unsigned long flags;
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struct dma_async_tx_descriptor *desc;
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dma_cookie_t cookie;
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if (is_tx) {
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dir = DMA_MEM_TO_DEV;
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chan = master->dma_tx;
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nents = tfr->tx_sg.nents;
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sgl = tfr->tx_sg.sgl;
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flags = 0 /* no tx interrupt */;
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} else {
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dir = DMA_DEV_TO_MEM;
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chan = master->dma_rx;
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nents = tfr->rx_sg.nents;
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sgl = tfr->rx_sg.sgl;
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flags = DMA_PREP_INTERRUPT;
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}
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/* prepare the channel */
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desc = dmaengine_prep_slave_sg(chan, sgl, nents, dir, flags);
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if (!desc)
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return -EINVAL;
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/* set callback for rx */
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if (!is_tx) {
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desc->callback = bcm2835_spi_dma_done;
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desc->callback_param = master;
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}
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/* submit it to DMA-engine */
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cookie = dmaengine_submit(desc);
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return dma_submit_error(cookie);
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}
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static inline int bcm2835_check_sg_length(struct sg_table *sgt)
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{
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int i;
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struct scatterlist *sgl;
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/* check that the sg entries are word-sized (except for last) */
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for_each_sg(sgt->sgl, sgl, (int)sgt->nents - 1, i) {
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if (sg_dma_len(sgl) % 4)
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return -EFAULT;
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}
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return 0;
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}
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static int bcm2835_spi_transfer_one_dma(struct spi_master *master,
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struct spi_device *spi,
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struct spi_transfer *tfr,
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u32 cs)
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{
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struct bcm2835_spi *bs = spi_master_get_devdata(master);
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int ret;
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/* check that the scatter gather segments are all a multiple of 4 */
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if (bcm2835_check_sg_length(&tfr->tx_sg) ||
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bcm2835_check_sg_length(&tfr->rx_sg)) {
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dev_warn_once(&spi->dev,
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"scatter gather segment length is not a multiple of 4 - falling back to interrupt mode\n");
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return bcm2835_spi_transfer_one_irq(master, spi, tfr, cs);
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}
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/* setup tx-DMA */
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ret = bcm2835_spi_prepare_sg(master, tfr, true);
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if (ret)
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return ret;
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/* start TX early */
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dma_async_issue_pending(master->dma_tx);
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/* mark as dma pending */
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bs->dma_pending = 1;
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/* set the DMA length */
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bcm2835_wr(bs, BCM2835_SPI_DLEN, tfr->len);
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/* start the HW */
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bcm2835_wr(bs, BCM2835_SPI_CS,
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cs | BCM2835_SPI_CS_TA | BCM2835_SPI_CS_DMAEN);
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/* setup rx-DMA late - to run transfers while
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* mapping of the rx buffers still takes place
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* this saves 10us or more.
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*/
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ret = bcm2835_spi_prepare_sg(master, tfr, false);
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if (ret) {
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/* need to reset on errors */
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dmaengine_terminate_all(master->dma_tx);
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bcm2835_spi_reset_hw(master);
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return ret;
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}
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/* start rx dma late */
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dma_async_issue_pending(master->dma_rx);
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/* wait for wakeup in framework */
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return 1;
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}
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static bool bcm2835_spi_can_dma(struct spi_master *master,
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struct spi_device *spi,
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struct spi_transfer *tfr)
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{
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/* only run for gpio_cs */
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if (!gpio_is_valid(spi->cs_gpio))
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return false;
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/* we start DMA efforts only on bigger transfers */
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if (tfr->len < BCM2835_SPI_DMA_MIN_LENGTH)
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return false;
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/* BCM2835_SPI_DLEN has defined a max transfer size as
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* 16 bit, so max is 65535
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* we can revisit this by using an alternative transfer
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* method - ideally this would get done without any more
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* interaction...
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*/
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if (tfr->len > 65535) {
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dev_warn_once(&spi->dev,
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"transfer size of %d too big for dma-transfer\n",
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tfr->len);
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return false;
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}
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/* if we run rx/tx_buf with word aligned addresses then we are OK */
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if ((((size_t)tfr->rx_buf & 3) == 0) &&
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(((size_t)tfr->tx_buf & 3) == 0))
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return true;
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/* otherwise we only allow transfers within the same page
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* to avoid wasting time on dma_mapping when it is not practical
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*/
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if (((size_t)tfr->tx_buf & (PAGE_SIZE - 1)) + tfr->len > PAGE_SIZE) {
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dev_warn_once(&spi->dev,
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"Unaligned spi tx-transfer bridging page\n");
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return false;
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}
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if (((size_t)tfr->rx_buf & (PAGE_SIZE - 1)) + tfr->len > PAGE_SIZE) {
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dev_warn_once(&spi->dev,
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"Unaligned spi rx-transfer bridging page\n");
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return false;
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}
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/* return OK */
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return true;
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}
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static void bcm2835_dma_release(struct spi_master *master)
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{
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if (master->dma_tx) {
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dmaengine_terminate_all(master->dma_tx);
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dma_release_channel(master->dma_tx);
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master->dma_tx = NULL;
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}
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if (master->dma_rx) {
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dmaengine_terminate_all(master->dma_rx);
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dma_release_channel(master->dma_rx);
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master->dma_rx = NULL;
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}
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}
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static void bcm2835_dma_init(struct spi_master *master, struct device *dev)
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{
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struct dma_slave_config slave_config;
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const __be32 *addr;
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dma_addr_t dma_reg_base;
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int ret;
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/* base address in dma-space */
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addr = of_get_address(master->dev.of_node, 0, NULL, NULL);
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if (!addr) {
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dev_err(dev, "could not get DMA-register address - not using dma mode\n");
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goto err;
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}
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dma_reg_base = be32_to_cpup(addr);
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/* get tx/rx dma */
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master->dma_tx = dma_request_slave_channel(dev, "tx");
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if (!master->dma_tx) {
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dev_err(dev, "no tx-dma configuration found - not using dma mode\n");
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goto err;
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}
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master->dma_rx = dma_request_slave_channel(dev, "rx");
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if (!master->dma_rx) {
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dev_err(dev, "no rx-dma configuration found - not using dma mode\n");
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goto err_release;
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}
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/* configure DMAs */
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slave_config.direction = DMA_MEM_TO_DEV;
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slave_config.dst_addr = (u32)(dma_reg_base + BCM2835_SPI_FIFO);
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slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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ret = dmaengine_slave_config(master->dma_tx, &slave_config);
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if (ret)
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goto err_config;
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slave_config.direction = DMA_DEV_TO_MEM;
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slave_config.src_addr = (u32)(dma_reg_base + BCM2835_SPI_FIFO);
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slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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ret = dmaengine_slave_config(master->dma_rx, &slave_config);
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if (ret)
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goto err_config;
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/* all went well, so set can_dma */
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master->can_dma = bcm2835_spi_can_dma;
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master->max_dma_len = 65535; /* limitation by BCM2835_SPI_DLEN */
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/* need to do TX AND RX DMA, so we need dummy buffers */
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master->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX;
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return;
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err_config:
|
|
dev_err(dev, "issue configuring dma: %d - not using DMA mode\n",
|
|
ret);
|
|
err_release:
|
|
bcm2835_dma_release(master);
|
|
err:
|
|
return;
|
|
}
|
|
|
|
static int bcm2835_spi_transfer_one_poll(struct spi_master *master,
|
|
struct spi_device *spi,
|
|
struct spi_transfer *tfr,
|
|
u32 cs,
|
|
unsigned long long xfer_time_us)
|
|
{
|
|
struct bcm2835_spi *bs = spi_master_get_devdata(master);
|
|
unsigned long timeout;
|
|
|
|
/* enable HW block without interrupts */
|
|
bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA);
|
|
|
|
/* fill in the fifo before timeout calculations
|
|
* if we are interrupted here, then the data is
|
|
* getting transferred by the HW while we are interrupted
|
|
*/
|
|
bcm2835_wr_fifo(bs);
|
|
|
|
/* set the timeout */
|
|
timeout = jiffies + BCM2835_SPI_POLLING_JIFFIES;
|
|
|
|
/* loop until finished the transfer */
|
|
while (bs->rx_len) {
|
|
/* fill in tx fifo with remaining data */
|
|
bcm2835_wr_fifo(bs);
|
|
|
|
/* read from fifo as much as possible */
|
|
bcm2835_rd_fifo(bs);
|
|
|
|
/* if there is still data pending to read
|
|
* then check the timeout
|
|
*/
|
|
if (bs->rx_len && time_after(jiffies, timeout)) {
|
|
dev_dbg_ratelimited(&spi->dev,
|
|
"timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n",
|
|
jiffies - timeout,
|
|
bs->tx_len, bs->rx_len);
|
|
/* fall back to interrupt mode */
|
|
return bcm2835_spi_transfer_one_irq(master, spi,
|
|
tfr, cs);
|
|
}
|
|
}
|
|
|
|
/* Transfer complete - reset SPI HW */
|
|
bcm2835_spi_reset_hw(master);
|
|
/* and return without waiting for completion */
|
|
return 0;
|
|
}
|
|
|
|
static int bcm2835_spi_transfer_one(struct spi_master *master,
|
|
struct spi_device *spi,
|
|
struct spi_transfer *tfr)
|
|
{
|
|
struct bcm2835_spi *bs = spi_master_get_devdata(master);
|
|
unsigned long spi_hz, clk_hz, cdiv;
|
|
unsigned long spi_used_hz;
|
|
unsigned long long xfer_time_us;
|
|
u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
|
|
|
|
/* set clock */
|
|
spi_hz = tfr->speed_hz;
|
|
clk_hz = clk_get_rate(bs->clk);
|
|
|
|
if (spi_hz >= clk_hz / 2) {
|
|
cdiv = 2; /* clk_hz/2 is the fastest we can go */
|
|
} else if (spi_hz) {
|
|
/* CDIV must be a multiple of two */
|
|
cdiv = DIV_ROUND_UP(clk_hz, spi_hz);
|
|
cdiv += (cdiv % 2);
|
|
|
|
if (cdiv >= 65536)
|
|
cdiv = 0; /* 0 is the slowest we can go */
|
|
} else {
|
|
cdiv = 0; /* 0 is the slowest we can go */
|
|
}
|
|
spi_used_hz = cdiv ? (clk_hz / cdiv) : (clk_hz / 65536);
|
|
bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv);
|
|
|
|
/* handle all the 3-wire mode */
|
|
if ((spi->mode & SPI_3WIRE) && (tfr->rx_buf))
|
|
cs |= BCM2835_SPI_CS_REN;
|
|
else
|
|
cs &= ~BCM2835_SPI_CS_REN;
|
|
|
|
/* for gpio_cs set dummy CS so that no HW-CS get changed
|
|
* we can not run this in bcm2835_spi_set_cs, as it does
|
|
* not get called for cs_gpio cases, so we need to do it here
|
|
*/
|
|
if (gpio_is_valid(spi->cs_gpio) || (spi->mode & SPI_NO_CS))
|
|
cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01;
|
|
|
|
/* set transmit buffers and length */
|
|
bs->tx_buf = tfr->tx_buf;
|
|
bs->rx_buf = tfr->rx_buf;
|
|
bs->tx_len = tfr->len;
|
|
bs->rx_len = tfr->len;
|
|
|
|
/* calculate the estimated time in us the transfer runs */
|
|
xfer_time_us = (unsigned long long)tfr->len
|
|
* 9 /* clocks/byte - SPI-HW waits 1 clock after each byte */
|
|
* 1000000;
|
|
do_div(xfer_time_us, spi_used_hz);
|
|
|
|
/* for short requests run polling*/
|
|
if (xfer_time_us <= BCM2835_SPI_POLLING_LIMIT_US)
|
|
return bcm2835_spi_transfer_one_poll(master, spi, tfr,
|
|
cs, xfer_time_us);
|
|
|
|
/* run in dma mode if conditions are right */
|
|
if (master->can_dma && bcm2835_spi_can_dma(master, spi, tfr))
|
|
return bcm2835_spi_transfer_one_dma(master, spi, tfr, cs);
|
|
|
|
/* run in interrupt-mode */
|
|
return bcm2835_spi_transfer_one_irq(master, spi, tfr, cs);
|
|
}
|
|
|
|
static int bcm2835_spi_prepare_message(struct spi_master *master,
|
|
struct spi_message *msg)
|
|
{
|
|
struct spi_device *spi = msg->spi;
|
|
struct bcm2835_spi *bs = spi_master_get_devdata(master);
|
|
u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
|
|
|
|
cs &= ~(BCM2835_SPI_CS_CPOL | BCM2835_SPI_CS_CPHA);
|
|
|
|
if (spi->mode & SPI_CPOL)
|
|
cs |= BCM2835_SPI_CS_CPOL;
|
|
if (spi->mode & SPI_CPHA)
|
|
cs |= BCM2835_SPI_CS_CPHA;
|
|
|
|
bcm2835_wr(bs, BCM2835_SPI_CS, cs);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void bcm2835_spi_handle_err(struct spi_master *master,
|
|
struct spi_message *msg)
|
|
{
|
|
struct bcm2835_spi *bs = spi_master_get_devdata(master);
|
|
|
|
/* if an error occurred and we have an active dma, then terminate */
|
|
if (bs->dma_pending) {
|
|
dmaengine_terminate_all(master->dma_tx);
|
|
dmaengine_terminate_all(master->dma_rx);
|
|
bs->dma_pending = 0;
|
|
}
|
|
/* and reset */
|
|
bcm2835_spi_reset_hw(master);
|
|
}
|
|
|
|
static void bcm2835_spi_set_cs(struct spi_device *spi, bool gpio_level)
|
|
{
|
|
/*
|
|
* we can assume that we are "native" as per spi_set_cs
|
|
* calling us ONLY when cs_gpio is not set
|
|
* we can also assume that we are CS < 3 as per bcm2835_spi_setup
|
|
* we would not get called because of error handling there.
|
|
* the level passed is the electrical level not enabled/disabled
|
|
* so it has to get translated back to enable/disable
|
|
* see spi_set_cs in spi.c for the implementation
|
|
*/
|
|
|
|
struct spi_master *master = spi->master;
|
|
struct bcm2835_spi *bs = spi_master_get_devdata(master);
|
|
u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
|
|
bool enable;
|
|
|
|
/* calculate the enable flag from the passed gpio_level */
|
|
enable = (spi->mode & SPI_CS_HIGH) ? gpio_level : !gpio_level;
|
|
|
|
/* set flags for "reverse" polarity in the registers */
|
|
if (spi->mode & SPI_CS_HIGH) {
|
|
/* set the correct CS-bits */
|
|
cs |= BCM2835_SPI_CS_CSPOL;
|
|
cs |= BCM2835_SPI_CS_CSPOL0 << spi->chip_select;
|
|
} else {
|
|
/* clean the CS-bits */
|
|
cs &= ~BCM2835_SPI_CS_CSPOL;
|
|
cs &= ~(BCM2835_SPI_CS_CSPOL0 << spi->chip_select);
|
|
}
|
|
|
|
/* select the correct chip_select depending on disabled/enabled */
|
|
if (enable) {
|
|
/* set cs correctly */
|
|
if (spi->mode & SPI_NO_CS) {
|
|
/* use the "undefined" chip-select */
|
|
cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01;
|
|
} else {
|
|
/* set the chip select */
|
|
cs &= ~(BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01);
|
|
cs |= spi->chip_select;
|
|
}
|
|
} else {
|
|
/* disable CSPOL which puts HW-CS into deselected state */
|
|
cs &= ~BCM2835_SPI_CS_CSPOL;
|
|
/* use the "undefined" chip-select as precaution */
|
|
cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01;
|
|
}
|
|
|
|
/* finally set the calculated flags in SPI_CS */
|
|
bcm2835_wr(bs, BCM2835_SPI_CS, cs);
|
|
}
|
|
|
|
static int chip_match_name(struct gpio_chip *chip, void *data)
|
|
{
|
|
return !strcmp(chip->label, data);
|
|
}
|
|
|
|
static int bcm2835_spi_setup(struct spi_device *spi)
|
|
{
|
|
int err;
|
|
struct gpio_chip *chip;
|
|
/*
|
|
* sanity checking the native-chipselects
|
|
*/
|
|
if (spi->mode & SPI_NO_CS)
|
|
return 0;
|
|
if (gpio_is_valid(spi->cs_gpio))
|
|
return 0;
|
|
if (spi->chip_select > 1) {
|
|
/* error in the case of native CS requested with CS > 1
|
|
* officially there is a CS2, but it is not documented
|
|
* which GPIO is connected with that...
|
|
*/
|
|
dev_err(&spi->dev,
|
|
"setup: only two native chip-selects are supported\n");
|
|
return -EINVAL;
|
|
}
|
|
/* now translate native cs to GPIO */
|
|
|
|
/* get the gpio chip for the base */
|
|
chip = gpiochip_find("pinctrl-bcm2835", chip_match_name);
|
|
if (!chip)
|
|
return 0;
|
|
|
|
/* and calculate the real CS */
|
|
spi->cs_gpio = chip->base + 8 - spi->chip_select;
|
|
|
|
/* and set up the "mode" and level */
|
|
dev_info(&spi->dev, "setting up native-CS%i as GPIO %i\n",
|
|
spi->chip_select, spi->cs_gpio);
|
|
|
|
/* set up GPIO as output and pull to the correct level */
|
|
err = gpio_direction_output(spi->cs_gpio,
|
|
(spi->mode & SPI_CS_HIGH) ? 0 : 1);
|
|
if (err) {
|
|
dev_err(&spi->dev,
|
|
"could not set CS%i gpio %i as output: %i",
|
|
spi->chip_select, spi->cs_gpio, err);
|
|
return err;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int bcm2835_spi_probe(struct platform_device *pdev)
|
|
{
|
|
struct spi_master *master;
|
|
struct bcm2835_spi *bs;
|
|
struct resource *res;
|
|
int err;
|
|
|
|
master = spi_alloc_master(&pdev->dev, sizeof(*bs));
|
|
if (!master) {
|
|
dev_err(&pdev->dev, "spi_alloc_master() failed\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, master);
|
|
|
|
master->mode_bits = BCM2835_SPI_MODE_BITS;
|
|
master->bits_per_word_mask = SPI_BPW_MASK(8);
|
|
master->num_chipselect = 3;
|
|
master->setup = bcm2835_spi_setup;
|
|
master->set_cs = bcm2835_spi_set_cs;
|
|
master->transfer_one = bcm2835_spi_transfer_one;
|
|
master->handle_err = bcm2835_spi_handle_err;
|
|
master->prepare_message = bcm2835_spi_prepare_message;
|
|
master->dev.of_node = pdev->dev.of_node;
|
|
|
|
bs = spi_master_get_devdata(master);
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
bs->regs = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(bs->regs)) {
|
|
err = PTR_ERR(bs->regs);
|
|
goto out_master_put;
|
|
}
|
|
|
|
bs->clk = devm_clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(bs->clk)) {
|
|
err = PTR_ERR(bs->clk);
|
|
dev_err(&pdev->dev, "could not get clk: %d\n", err);
|
|
goto out_master_put;
|
|
}
|
|
|
|
bs->irq = platform_get_irq(pdev, 0);
|
|
if (bs->irq <= 0) {
|
|
dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq);
|
|
err = bs->irq ? bs->irq : -ENODEV;
|
|
goto out_master_put;
|
|
}
|
|
|
|
clk_prepare_enable(bs->clk);
|
|
|
|
bcm2835_dma_init(master, &pdev->dev);
|
|
|
|
/* initialise the hardware with the default polarities */
|
|
bcm2835_wr(bs, BCM2835_SPI_CS,
|
|
BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
|
|
|
|
err = devm_request_irq(&pdev->dev, bs->irq, bcm2835_spi_interrupt, 0,
|
|
dev_name(&pdev->dev), master);
|
|
if (err) {
|
|
dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
|
|
goto out_clk_disable;
|
|
}
|
|
|
|
err = devm_spi_register_master(&pdev->dev, master);
|
|
if (err) {
|
|
dev_err(&pdev->dev, "could not register SPI master: %d\n", err);
|
|
goto out_clk_disable;
|
|
}
|
|
|
|
return 0;
|
|
|
|
out_clk_disable:
|
|
clk_disable_unprepare(bs->clk);
|
|
out_master_put:
|
|
spi_master_put(master);
|
|
return err;
|
|
}
|
|
|
|
static int bcm2835_spi_remove(struct platform_device *pdev)
|
|
{
|
|
struct spi_master *master = platform_get_drvdata(pdev);
|
|
struct bcm2835_spi *bs = spi_master_get_devdata(master);
|
|
|
|
/* Clear FIFOs, and disable the HW block */
|
|
bcm2835_wr(bs, BCM2835_SPI_CS,
|
|
BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
|
|
|
|
clk_disable_unprepare(bs->clk);
|
|
|
|
bcm2835_dma_release(master);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id bcm2835_spi_match[] = {
|
|
{ .compatible = "brcm,bcm2835-spi", },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, bcm2835_spi_match);
|
|
|
|
static struct platform_driver bcm2835_spi_driver = {
|
|
.driver = {
|
|
.name = DRV_NAME,
|
|
.of_match_table = bcm2835_spi_match,
|
|
},
|
|
.probe = bcm2835_spi_probe,
|
|
.remove = bcm2835_spi_remove,
|
|
};
|
|
module_platform_driver(bcm2835_spi_driver);
|
|
|
|
MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835");
|
|
MODULE_AUTHOR("Chris Boot <bootc@bootc.net>");
|
|
MODULE_LICENSE("GPL v2");
|