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66810912fd
kernel version describes module state more accurately. hence remove chcr versioning. Signed-off-by: Vinay Kumar Yadav <vinay.yadav@chelsio.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
312 lines
7.8 KiB
C
312 lines
7.8 KiB
C
/*
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* This file is part of the Chelsio T4/T5/T6 Ethernet driver for Linux.
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*
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* Copyright (C) 2011-2016 Chelsio Communications. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation.
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*
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* Written and Maintained by:
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* Manoj Malviya (manojmalviya@chelsio.com)
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* Atul Gupta (atul.gupta@chelsio.com)
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* Jitendra Lulla (jlulla@chelsio.com)
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* Yeshaswi M R Gowda (yeshaswi@chelsio.com)
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* Harsh Jain (harsh@chelsio.com)
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/skbuff.h>
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#include <crypto/aes.h>
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#include <crypto/hash.h>
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#include "t4_msg.h"
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#include "chcr_core.h"
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#include "cxgb4_uld.h"
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static struct chcr_driver_data drv_data;
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typedef int (*chcr_handler_func)(struct adapter *adap, unsigned char *input);
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static int cpl_fw6_pld_handler(struct adapter *adap, unsigned char *input);
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static void *chcr_uld_add(const struct cxgb4_lld_info *lld);
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static int chcr_uld_state_change(void *handle, enum cxgb4_state state);
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static chcr_handler_func work_handlers[NUM_CPL_CMDS] = {
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[CPL_FW6_PLD] = cpl_fw6_pld_handler,
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};
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static struct cxgb4_uld_info chcr_uld_info = {
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.name = DRV_MODULE_NAME,
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.nrxq = MAX_ULD_QSETS,
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/* Max ntxq will be derived from fw config file*/
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.rxq_size = 1024,
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.add = chcr_uld_add,
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.state_change = chcr_uld_state_change,
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.rx_handler = chcr_uld_rx_handler,
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};
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static void detach_work_fn(struct work_struct *work)
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{
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struct chcr_dev *dev;
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dev = container_of(work, struct chcr_dev, detach_work.work);
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if (atomic_read(&dev->inflight)) {
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dev->wqretry--;
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if (dev->wqretry) {
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pr_debug("Request Inflight Count %d\n",
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atomic_read(&dev->inflight));
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schedule_delayed_work(&dev->detach_work, WQ_DETACH_TM);
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} else {
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WARN(1, "CHCR:%d request Still Pending\n",
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atomic_read(&dev->inflight));
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complete(&dev->detach_comp);
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}
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} else {
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complete(&dev->detach_comp);
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}
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}
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struct uld_ctx *assign_chcr_device(void)
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{
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struct uld_ctx *u_ctx = NULL;
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/*
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* When multiple devices are present in system select
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* device in round-robin fashion for crypto operations
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* Although One session must use the same device to
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* maintain request-response ordering.
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*/
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mutex_lock(&drv_data.drv_mutex);
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if (!list_empty(&drv_data.act_dev)) {
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u_ctx = drv_data.last_dev;
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if (list_is_last(&drv_data.last_dev->entry, &drv_data.act_dev))
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drv_data.last_dev = list_first_entry(&drv_data.act_dev,
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struct uld_ctx, entry);
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else
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drv_data.last_dev =
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list_next_entry(drv_data.last_dev, entry);
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}
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mutex_unlock(&drv_data.drv_mutex);
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return u_ctx;
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}
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static void chcr_dev_add(struct uld_ctx *u_ctx)
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{
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struct chcr_dev *dev;
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dev = &u_ctx->dev;
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dev->state = CHCR_ATTACH;
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atomic_set(&dev->inflight, 0);
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mutex_lock(&drv_data.drv_mutex);
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list_move(&u_ctx->entry, &drv_data.act_dev);
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if (!drv_data.last_dev)
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drv_data.last_dev = u_ctx;
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mutex_unlock(&drv_data.drv_mutex);
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}
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static void chcr_dev_init(struct uld_ctx *u_ctx)
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{
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struct chcr_dev *dev;
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dev = &u_ctx->dev;
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spin_lock_init(&dev->lock_chcr_dev);
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INIT_DELAYED_WORK(&dev->detach_work, detach_work_fn);
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init_completion(&dev->detach_comp);
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dev->state = CHCR_INIT;
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dev->wqretry = WQ_RETRY;
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atomic_inc(&drv_data.dev_count);
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atomic_set(&dev->inflight, 0);
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mutex_lock(&drv_data.drv_mutex);
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list_add_tail(&u_ctx->entry, &drv_data.inact_dev);
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mutex_unlock(&drv_data.drv_mutex);
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}
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static int chcr_dev_move(struct uld_ctx *u_ctx)
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{
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mutex_lock(&drv_data.drv_mutex);
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if (drv_data.last_dev == u_ctx) {
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if (list_is_last(&drv_data.last_dev->entry, &drv_data.act_dev))
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drv_data.last_dev = list_first_entry(&drv_data.act_dev,
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struct uld_ctx, entry);
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else
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drv_data.last_dev =
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list_next_entry(drv_data.last_dev, entry);
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}
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list_move(&u_ctx->entry, &drv_data.inact_dev);
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if (list_empty(&drv_data.act_dev))
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drv_data.last_dev = NULL;
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atomic_dec(&drv_data.dev_count);
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mutex_unlock(&drv_data.drv_mutex);
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return 0;
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}
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static int cpl_fw6_pld_handler(struct adapter *adap,
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unsigned char *input)
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{
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struct crypto_async_request *req;
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struct cpl_fw6_pld *fw6_pld;
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u32 ack_err_status = 0;
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int error_status = 0;
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fw6_pld = (struct cpl_fw6_pld *)input;
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req = (struct crypto_async_request *)(uintptr_t)be64_to_cpu(
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fw6_pld->data[1]);
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ack_err_status =
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ntohl(*(__be32 *)((unsigned char *)&fw6_pld->data[0] + 4));
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if (CHK_MAC_ERR_BIT(ack_err_status) || CHK_PAD_ERR_BIT(ack_err_status))
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error_status = -EBADMSG;
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/* call completion callback with failure status */
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if (req) {
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error_status = chcr_handle_resp(req, input, error_status);
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} else {
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pr_err("Incorrect request address from the firmware\n");
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return -EFAULT;
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}
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if (error_status)
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atomic_inc(&adap->chcr_stats.error);
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return 0;
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}
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int chcr_send_wr(struct sk_buff *skb)
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{
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return cxgb4_crypto_send(skb->dev, skb);
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}
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static void *chcr_uld_add(const struct cxgb4_lld_info *lld)
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{
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struct uld_ctx *u_ctx;
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/* Create the device and add it in the device list */
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pr_info_once("%s\n", DRV_DESC);
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if (!(lld->ulp_crypto & ULP_CRYPTO_LOOKASIDE))
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return ERR_PTR(-EOPNOTSUPP);
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/* Create the device and add it in the device list */
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u_ctx = kzalloc(sizeof(*u_ctx), GFP_KERNEL);
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if (!u_ctx) {
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u_ctx = ERR_PTR(-ENOMEM);
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goto out;
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}
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u_ctx->lldi = *lld;
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chcr_dev_init(u_ctx);
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out:
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return u_ctx;
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}
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int chcr_uld_rx_handler(void *handle, const __be64 *rsp,
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const struct pkt_gl *pgl)
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{
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struct uld_ctx *u_ctx = (struct uld_ctx *)handle;
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struct chcr_dev *dev = &u_ctx->dev;
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struct adapter *adap = padap(dev);
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const struct cpl_fw6_pld *rpl = (struct cpl_fw6_pld *)rsp;
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if (!work_handlers[rpl->opcode]) {
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pr_err("Unsupported opcode %d received\n", rpl->opcode);
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return 0;
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}
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if (!pgl)
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work_handlers[rpl->opcode](adap, (unsigned char *)&rsp[1]);
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else
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work_handlers[rpl->opcode](adap, pgl->va);
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return 0;
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}
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static void chcr_detach_device(struct uld_ctx *u_ctx)
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{
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struct chcr_dev *dev = &u_ctx->dev;
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if (dev->state == CHCR_DETACH) {
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pr_debug("Detached Event received for already detach device\n");
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return;
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}
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dev->state = CHCR_DETACH;
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if (atomic_read(&dev->inflight) != 0) {
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schedule_delayed_work(&dev->detach_work, WQ_DETACH_TM);
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wait_for_completion(&dev->detach_comp);
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}
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// Move u_ctx to inactive_dev list
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chcr_dev_move(u_ctx);
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}
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static int chcr_uld_state_change(void *handle, enum cxgb4_state state)
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{
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struct uld_ctx *u_ctx = handle;
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int ret = 0;
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switch (state) {
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case CXGB4_STATE_UP:
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if (u_ctx->dev.state != CHCR_INIT) {
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// ALready Initialised.
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return 0;
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}
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chcr_dev_add(u_ctx);
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ret = start_crypto();
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break;
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case CXGB4_STATE_DETACH:
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chcr_detach_device(u_ctx);
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if (!atomic_read(&drv_data.dev_count))
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stop_crypto();
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break;
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case CXGB4_STATE_START_RECOVERY:
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case CXGB4_STATE_DOWN:
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default:
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break;
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}
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return ret;
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}
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static int __init chcr_crypto_init(void)
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{
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INIT_LIST_HEAD(&drv_data.act_dev);
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INIT_LIST_HEAD(&drv_data.inact_dev);
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atomic_set(&drv_data.dev_count, 0);
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mutex_init(&drv_data.drv_mutex);
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drv_data.last_dev = NULL;
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cxgb4_register_uld(CXGB4_ULD_CRYPTO, &chcr_uld_info);
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return 0;
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}
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static void __exit chcr_crypto_exit(void)
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{
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struct uld_ctx *u_ctx, *tmp;
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struct adapter *adap;
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stop_crypto();
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cxgb4_unregister_uld(CXGB4_ULD_CRYPTO);
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/* Remove all devices from list */
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mutex_lock(&drv_data.drv_mutex);
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list_for_each_entry_safe(u_ctx, tmp, &drv_data.act_dev, entry) {
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adap = padap(&u_ctx->dev);
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memset(&adap->chcr_stats, 0, sizeof(adap->chcr_stats));
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list_del(&u_ctx->entry);
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kfree(u_ctx);
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}
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list_for_each_entry_safe(u_ctx, tmp, &drv_data.inact_dev, entry) {
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adap = padap(&u_ctx->dev);
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memset(&adap->chcr_stats, 0, sizeof(adap->chcr_stats));
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list_del(&u_ctx->entry);
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kfree(u_ctx);
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}
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mutex_unlock(&drv_data.drv_mutex);
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}
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module_init(chcr_crypto_init);
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module_exit(chcr_crypto_exit);
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MODULE_DESCRIPTION("Crypto Co-processor for Chelsio Terminator cards.");
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Chelsio Communications");
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