Chris Wilson 48004881f6 drm/i915: Mark CPU cache as dirty when used for rendering ... On LLC, or even snooped, machines rendering via the GPU ends up in the CPU cache. This cacheline dirt also needs to be flushed to main memory when moving to an incoherent domain, such as the display's scanout engine. Mostly, this happens because either the object is marked as dirty from its first use or is avoided by setting the object into the display domain from the start. v2: Treat WT as not requiring a clflush prior to use on the display engine as well. Fixes: 0f71979ab7 ("drm/i915: Performed deferred clflush inside set-cache-level") References: https://bugs.freedesktop.org/show_bug.cgi?id=95414 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: <stable@vger.kernel.org> # v4.0+ Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20161107165204.7008-1-chris@chris-wilson.co.uk (cherry picked from commit 7aa6ca61ee) Signed-off-by: Jani Nikula <jani.nikula@intel.com>		2016-11-11 10:04:30 +02:00
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drm	drm/i915: Mark CPU cache as dirty when used for rendering	2016-11-11 10:04:30 +02:00
host1x	drm/tegra: dsi: Enhance runtime power management	2016-08-24 15:58:57 +02:00
ipu-v3	gpu: ipu-v3: Use ERR_CAST instead of ERR_PTR(PTR_ERR())	2016-10-17 08:21:53 +02:00
vga	vgaarbiter: rst-ifiy and polish kerneldoc	2016-08-16 18:49:56 +02:00
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