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8bd26e3a7e
The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost and complications. For example, the fix in
commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time")
is a good example of the nasty type of bugs that can be created
with improper use of the various __init prefixes.
After a discussion on LKML[1] it was decided that cpuinit should go
the way of devinit and be phased out. Once all the users are gone,
we can then finally remove the macros themselves from linux/init.h.
Note that some harmless section mismatch warnings may result, since
notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
and are flagged as __cpuinit -- so if we remove the __cpuinit from
the arch specific callers, we will also get section mismatch warnings.
As an intermediate step, we intend to turn the linux/init.h cpuinit
related content into no-ops as early as possible, since that will get
rid of these warnings. In any case, they are temporary and harmless.
This removes all the ARM uses of the __cpuinit macros from C code,
and all __CPUINIT from assembly code. It also had two ".previous"
section statements that were paired off against __CPUINIT
(aka .section ".cpuinit.text") that also get removed here.
[1] https://lkml.org/lkml/2013/5/20/589
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
260 lines
7.4 KiB
ArmAsm
260 lines
7.4 KiB
ArmAsm
/*
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* linux/arch/arm/kernel/head-nommu.S
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*
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* Copyright (C) 1994-2002 Russell King
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* Copyright (C) 2003-2006 Hyok S. Choi
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Common kernel startup code (non-paged MM)
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*
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/ptrace.h>
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#include <asm/asm-offsets.h>
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#include <asm/memory.h>
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#include <asm/cp15.h>
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#include <asm/thread_info.h>
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#include <asm/v7m.h>
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#include <asm/mpu.h>
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#include <asm/page.h>
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/*
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* Kernel startup entry point.
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* ---------------------------
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*
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* This is normally called from the decompressor code. The requirements
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* are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
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* r1 = machine nr.
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*
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* See linux/arch/arm/tools/mach-types for the complete list of machine
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* numbers for r1.
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*
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*/
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__HEAD
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#ifdef CONFIG_CPU_THUMBONLY
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.thumb
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ENTRY(stext)
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#else
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.arm
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ENTRY(stext)
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THUMB( adr r9, BSYM(1f) ) @ Kernel is always entered in ARM.
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THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
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THUMB( .thumb ) @ switch to Thumb now.
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THUMB(1: )
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#endif
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setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
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@ and irqs disabled
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#if defined(CONFIG_CPU_CP15)
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mrc p15, 0, r9, c0, c0 @ get processor id
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#elif defined(CONFIG_CPU_V7M)
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ldr r9, =BASEADDR_V7M_SCB
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ldr r9, [r9, V7M_SCB_CPUID]
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#else
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ldr r9, =CONFIG_PROCESSOR_ID
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#endif
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bl __lookup_processor_type @ r5=procinfo r9=cpuid
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movs r10, r5 @ invalid processor (r5=0)?
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beq __error_p @ yes, error 'p'
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#ifdef CONFIG_ARM_MPU
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/* Calculate the size of a region covering just the kernel */
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ldr r5, =PHYS_OFFSET @ Region start: PHYS_OFFSET
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ldr r6, =(_end) @ Cover whole kernel
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sub r6, r6, r5 @ Minimum size of region to map
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clz r6, r6 @ Region size must be 2^N...
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rsb r6, r6, #31 @ ...so round up region size
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lsl r6, r6, #MPU_RSR_SZ @ Put size in right field
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orr r6, r6, #(1 << MPU_RSR_EN) @ Set region enabled bit
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bl __setup_mpu
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#endif
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ldr r13, =__mmap_switched @ address to jump to after
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@ initialising sctlr
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adr lr, BSYM(1f) @ return (PIC) address
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ARM( add pc, r10, #PROCINFO_INITFUNC )
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THUMB( add r12, r10, #PROCINFO_INITFUNC )
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THUMB( mov pc, r12 )
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1: b __after_proc_init
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ENDPROC(stext)
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#ifdef CONFIG_SMP
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ENTRY(secondary_startup)
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/*
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* Common entry point for secondary CPUs.
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*
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* Ensure that we're in SVC mode, and IRQs are disabled. Lookup
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* the processor type - there is no need to check the machine type
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* as it has already been validated by the primary processor.
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*/
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setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9
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#ifndef CONFIG_CPU_CP15
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ldr r9, =CONFIG_PROCESSOR_ID
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#else
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mrc p15, 0, r9, c0, c0 @ get processor id
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#endif
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bl __lookup_processor_type @ r5=procinfo r9=cpuid
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movs r10, r5 @ invalid processor?
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beq __error_p @ yes, error 'p'
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adr r4, __secondary_data
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ldmia r4, {r7, r12}
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#ifdef CONFIG_ARM_MPU
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/* Use MPU region info supplied by __cpu_up */
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ldr r6, [r7] @ get secondary_data.mpu_szr
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bl __setup_mpu @ Initialize the MPU
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#endif
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adr lr, BSYM(__after_proc_init) @ return address
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mov r13, r12 @ __secondary_switched address
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ARM( add pc, r10, #PROCINFO_INITFUNC )
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THUMB( add r12, r10, #PROCINFO_INITFUNC )
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THUMB( mov pc, r12 )
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ENDPROC(secondary_startup)
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ENTRY(__secondary_switched)
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ldr sp, [r7, #8] @ set up the stack pointer
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mov fp, #0
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b secondary_start_kernel
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ENDPROC(__secondary_switched)
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.type __secondary_data, %object
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__secondary_data:
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.long secondary_data
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.long __secondary_switched
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#endif /* CONFIG_SMP */
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/*
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* Set the Control Register and Read the process ID.
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*/
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__after_proc_init:
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#ifdef CONFIG_CPU_CP15
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/*
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* CP15 system control register value returned in r0 from
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* the CPU init function.
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*/
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#if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6
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orr r0, r0, #CR_A
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#else
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bic r0, r0, #CR_A
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#endif
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#ifdef CONFIG_CPU_DCACHE_DISABLE
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bic r0, r0, #CR_C
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#endif
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#ifdef CONFIG_CPU_BPREDICT_DISABLE
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bic r0, r0, #CR_Z
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#endif
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#ifdef CONFIG_CPU_ICACHE_DISABLE
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bic r0, r0, #CR_I
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#endif
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#ifdef CONFIG_CPU_HIGH_VECTOR
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orr r0, r0, #CR_V
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#else
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bic r0, r0, #CR_V
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#endif
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mcr p15, 0, r0, c1, c0, 0 @ write control reg
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#endif /* CONFIG_CPU_CP15 */
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mov pc, r13
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ENDPROC(__after_proc_init)
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.ltorg
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#ifdef CONFIG_ARM_MPU
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/* Set which MPU region should be programmed */
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.macro set_region_nr tmp, rgnr
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mov \tmp, \rgnr @ Use static region numbers
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mcr p15, 0, \tmp, c6, c2, 0 @ Write RGNR
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.endm
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/* Setup a single MPU region, either D or I side (D-side for unified) */
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.macro setup_region bar, acr, sr, side = MPU_DATA_SIDE
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mcr p15, 0, \bar, c6, c1, (0 + \side) @ I/DRBAR
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mcr p15, 0, \acr, c6, c1, (4 + \side) @ I/DRACR
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mcr p15, 0, \sr, c6, c1, (2 + \side) @ I/DRSR
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.endm
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/*
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* Setup the MPU and initial MPU Regions. We create the following regions:
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* Region 0: Use this for probing the MPU details, so leave disabled.
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* Region 1: Background region - covers the whole of RAM as strongly ordered
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* Region 2: Normal, Shared, cacheable for RAM. From PHYS_OFFSET, size from r6
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* Region 3: Normal, shared, inaccessible from PL0 to protect the vectors page
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*
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* r6: Value to be written to DRSR (and IRSR if required) for MPU_RAM_REGION
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*/
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ENTRY(__setup_mpu)
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/* Probe for v7 PMSA compliance */
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mrc p15, 0, r0, c0, c1, 4 @ Read ID_MMFR0
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and r0, r0, #(MMFR0_PMSA) @ PMSA field
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teq r0, #(MMFR0_PMSAv7) @ PMSA v7
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bne __error_p @ Fail: ARM_MPU on NOT v7 PMSA
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/* Determine whether the D/I-side memory map is unified. We set the
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* flags here and continue to use them for the rest of this function */
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mrc p15, 0, r0, c0, c0, 4 @ MPUIR
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ands r5, r0, #MPUIR_DREGION_SZMASK @ 0 size d region => No MPU
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beq __error_p @ Fail: ARM_MPU and no MPU
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tst r0, #MPUIR_nU @ MPUIR_nU = 0 for unified
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/* Setup second region first to free up r6 */
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set_region_nr r0, #MPU_RAM_REGION
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isb
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/* Full access from PL0, PL1, shared for CONFIG_SMP, cacheable */
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ldr r0, =PHYS_OFFSET @ RAM starts at PHYS_OFFSET
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ldr r5,=(MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL)
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setup_region r0, r5, r6, MPU_DATA_SIDE @ PHYS_OFFSET, shared, enabled
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beq 1f @ Memory-map not unified
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setup_region r0, r5, r6, MPU_INSTR_SIDE @ PHYS_OFFSET, shared, enabled
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1: isb
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/* First/background region */
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set_region_nr r0, #MPU_BG_REGION
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isb
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/* Execute Never, strongly ordered, inaccessible to PL0, rw PL1 */
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mov r0, #0 @ BG region starts at 0x0
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ldr r5,=(MPU_ACR_XN | MPU_RGN_STRONGLY_ORDERED | MPU_AP_PL1RW_PL0NA)
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mov r6, #MPU_RSR_ALL_MEM @ 4GB region, enabled
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setup_region r0, r5, r6, MPU_DATA_SIDE @ 0x0, BG region, enabled
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beq 2f @ Memory-map not unified
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setup_region r0, r5, r6, MPU_INSTR_SIDE @ 0x0, BG region, enabled
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2: isb
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/* Vectors region */
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set_region_nr r0, #MPU_VECTORS_REGION
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isb
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/* Shared, inaccessible to PL0, rw PL1 */
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mov r0, #CONFIG_VECTORS_BASE @ Cover from VECTORS_BASE
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ldr r5,=(MPU_AP_PL1RW_PL0NA | MPU_RGN_NORMAL)
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/* Writing N to bits 5:1 (RSR_SZ) --> region size 2^N+1 */
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mov r6, #(((PAGE_SHIFT - 1) << MPU_RSR_SZ) | 1 << MPU_RSR_EN)
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setup_region r0, r5, r6, MPU_DATA_SIDE @ VECTORS_BASE, PL0 NA, enabled
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beq 3f @ Memory-map not unified
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setup_region r0, r5, r6, MPU_INSTR_SIDE @ VECTORS_BASE, PL0 NA, enabled
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3: isb
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/* Enable the MPU */
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mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR
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bic r0, r0, #CR_BR @ Disable the 'default mem-map'
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orr r0, r0, #CR_M @ Set SCTRL.M (MPU on)
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mcr p15, 0, r0, c1, c0, 0 @ Enable MPU
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isb
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mov pc,lr
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ENDPROC(__setup_mpu)
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#endif
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#include "head-common.S"
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