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5a3ae7b314
The ftrace trampoline code (which deals with modules loaded out of
BL range of the core kernel) uses plt_entries_equal() to check whether
the per-module trampoline equals a zero buffer, to decide whether the
trampoline has already been initialized.
This triggers a BUG() in the opcode manipulation code, since we end
up checking the ADRP offset of a 0x0 opcode, which is not an ADRP
instruction.
So instead, add a helper to check whether a PLT is initialized, and
call that from the frace code.
Cc: <stable@vger.kernel.org> # v5.0
Fixes: bdb85cd1d2 ("arm64/module: switch to ADRP/ADD sequences for PLT entries")
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
82 lines
2.3 KiB
C
82 lines
2.3 KiB
C
/*
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_MODULE_H
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#define __ASM_MODULE_H
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#include <asm-generic/module.h>
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#define MODULE_ARCH_VERMAGIC "aarch64"
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#ifdef CONFIG_ARM64_MODULE_PLTS
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struct mod_plt_sec {
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int plt_shndx;
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int plt_num_entries;
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int plt_max_entries;
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};
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struct mod_arch_specific {
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struct mod_plt_sec core;
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struct mod_plt_sec init;
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/* for CONFIG_DYNAMIC_FTRACE */
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struct plt_entry *ftrace_trampoline;
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};
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#endif
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u64 module_emit_plt_entry(struct module *mod, Elf64_Shdr *sechdrs,
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void *loc, const Elf64_Rela *rela,
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Elf64_Sym *sym);
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u64 module_emit_veneer_for_adrp(struct module *mod, Elf64_Shdr *sechdrs,
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void *loc, u64 val);
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#ifdef CONFIG_RANDOMIZE_BASE
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extern u64 module_alloc_base;
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#else
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#define module_alloc_base ((u64)_etext - MODULES_VSIZE)
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#endif
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struct plt_entry {
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/*
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* A program that conforms to the AArch64 Procedure Call Standard
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* (AAPCS64) must assume that a veneer that alters IP0 (x16) and/or
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* IP1 (x17) may be inserted at any branch instruction that is
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* exposed to a relocation that supports long branches. Since that
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* is exactly what we are dealing with here, we are free to use x16
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* as a scratch register in the PLT veneers.
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*/
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__le32 adrp; /* adrp x16, .... */
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__le32 add; /* add x16, x16, #0x.... */
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__le32 br; /* br x16 */
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};
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static inline bool is_forbidden_offset_for_adrp(void *place)
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{
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return IS_ENABLED(CONFIG_ARM64_ERRATUM_843419) &&
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cpus_have_const_cap(ARM64_WORKAROUND_843419) &&
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((u64)place & 0xfff) >= 0xff8;
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}
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struct plt_entry get_plt_entry(u64 dst, void *pc);
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bool plt_entries_equal(const struct plt_entry *a, const struct plt_entry *b);
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static inline bool plt_entry_is_initialized(const struct plt_entry *e)
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{
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return e->adrp || e->add || e->br;
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}
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#endif /* __ASM_MODULE_H */
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