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DG1 does some additional pcode/uncore handshaking at boot time; this handshaking must complete before various other pcode commands are effective and before general work is submitted to the GPU. We need to poll a new pcode mailbox during startup until it reports that this handshaking is complete. The bspec doesn't give guidance on how long we may need to wait for this handshaking to complete. For now, let's just set a really long timeout; if we still don't get a completion status by the end of that timeout, we'll just continue on and hope for the best. v2 (Lucas): Rename macros to make clear the relation between command and result (requested by José) Bspec: 52065 Cc: Clinton Taylor <Clinton.A.Taylor@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201001063917.3133475-2-lucas.demarchi@intel.com
144 lines
3.9 KiB
C
144 lines
3.9 KiB
C
/* SPDX-License-Identifier: MIT */
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#ifndef _INTEL_SIDEBAND_H_
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#define _INTEL_SIDEBAND_H_
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#include <linux/bitops.h>
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#include <linux/types.h>
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struct drm_i915_private;
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enum pipe;
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enum intel_sbi_destination {
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SBI_ICLK,
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SBI_MPHY,
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};
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enum {
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VLV_IOSF_SB_BUNIT,
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VLV_IOSF_SB_CCK,
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VLV_IOSF_SB_CCU,
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VLV_IOSF_SB_DPIO,
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VLV_IOSF_SB_FLISDSI,
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VLV_IOSF_SB_GPIO,
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VLV_IOSF_SB_NC,
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VLV_IOSF_SB_PUNIT,
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};
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void vlv_iosf_sb_get(struct drm_i915_private *i915, unsigned long ports);
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u32 vlv_iosf_sb_read(struct drm_i915_private *i915, u8 port, u32 reg);
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void vlv_iosf_sb_write(struct drm_i915_private *i915,
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u8 port, u32 reg, u32 val);
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void vlv_iosf_sb_put(struct drm_i915_private *i915, unsigned long ports);
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static inline void vlv_bunit_get(struct drm_i915_private *i915)
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{
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vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_BUNIT));
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}
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u32 vlv_bunit_read(struct drm_i915_private *i915, u32 reg);
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void vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val);
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static inline void vlv_bunit_put(struct drm_i915_private *i915)
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{
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vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_BUNIT));
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}
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static inline void vlv_cck_get(struct drm_i915_private *i915)
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{
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vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCK));
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}
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u32 vlv_cck_read(struct drm_i915_private *i915, u32 reg);
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void vlv_cck_write(struct drm_i915_private *i915, u32 reg, u32 val);
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static inline void vlv_cck_put(struct drm_i915_private *i915)
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{
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vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCK));
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}
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static inline void vlv_ccu_get(struct drm_i915_private *i915)
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{
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vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCU));
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}
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u32 vlv_ccu_read(struct drm_i915_private *i915, u32 reg);
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void vlv_ccu_write(struct drm_i915_private *i915, u32 reg, u32 val);
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static inline void vlv_ccu_put(struct drm_i915_private *i915)
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{
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vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCU));
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}
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static inline void vlv_dpio_get(struct drm_i915_private *i915)
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{
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vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_DPIO));
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}
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u32 vlv_dpio_read(struct drm_i915_private *i915, enum pipe pipe, int reg);
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void vlv_dpio_write(struct drm_i915_private *i915,
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enum pipe pipe, int reg, u32 val);
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static inline void vlv_dpio_put(struct drm_i915_private *i915)
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{
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vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_DPIO));
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}
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static inline void vlv_flisdsi_get(struct drm_i915_private *i915)
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{
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vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_FLISDSI));
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}
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u32 vlv_flisdsi_read(struct drm_i915_private *i915, u32 reg);
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void vlv_flisdsi_write(struct drm_i915_private *i915, u32 reg, u32 val);
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static inline void vlv_flisdsi_put(struct drm_i915_private *i915)
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{
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vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_FLISDSI));
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}
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static inline void vlv_nc_get(struct drm_i915_private *i915)
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{
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vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_NC));
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}
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u32 vlv_nc_read(struct drm_i915_private *i915, u8 addr);
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static inline void vlv_nc_put(struct drm_i915_private *i915)
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{
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vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_NC));
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}
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static inline void vlv_punit_get(struct drm_i915_private *i915)
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{
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vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_PUNIT));
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}
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u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr);
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int vlv_punit_write(struct drm_i915_private *i915, u32 addr, u32 val);
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static inline void vlv_punit_put(struct drm_i915_private *i915)
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{
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vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_PUNIT));
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}
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u32 intel_sbi_read(struct drm_i915_private *i915, u16 reg,
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enum intel_sbi_destination destination);
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void intel_sbi_write(struct drm_i915_private *i915, u16 reg, u32 value,
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enum intel_sbi_destination destination);
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int sandybridge_pcode_read(struct drm_i915_private *i915, u32 mbox,
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u32 *val, u32 *val1);
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int sandybridge_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox,
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u32 val, int fast_timeout_us,
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int slow_timeout_ms);
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#define sandybridge_pcode_write(i915, mbox, val) \
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sandybridge_pcode_write_timeout(i915, mbox, val, 500, 0)
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int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
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u32 reply_mask, u32 reply, int timeout_base_ms);
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void intel_pcode_init(struct drm_i915_private *i915);
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#endif /* _INTEL_SIDEBAND_H */
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