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This is an assembler implementation of the SHA1 algorithm using the Supplemental SSE3 (SSSE3) instructions or, when available, the Advanced Vector Extensions (AVX). Testing with the tcrypt module shows the raw hash performance is up to 2.3 times faster than the C implementation, using 8k data blocks on a Core 2 Duo T5500. For the smalest data set (16 byte) it is still 25% faster. Since this implementation uses SSE/YMM registers it cannot safely be used in every situation, e.g. while an IRQ interrupts a kernel thread. The implementation falls back to the generic SHA1 variant, if using the SSE/YMM registers is not possible. With this algorithm I was able to increase the throughput of a single IPsec link from 344 Mbit/s to 464 Mbit/s on a Core 2 Quad CPU using the SSSE3 variant -- a speedup of +34.8%. Saving and restoring SSE/YMM state might make the actual throughput fluctuate when there are FPU intensive userland applications running. For example, meassuring the performance using iperf2 directly on the machine under test gives wobbling numbers because iperf2 uses the FPU for each packet to check if the reporting interval has expired (in the above test I got min/max/avg: 402/484/464 MBit/s). Using this algorithm on a IPsec gateway gives much more reasonable and stable numbers, albeit not as high as in the directly connected case. Here is the result from an RFC 2544 test run with a EXFO Packet Blazer FTB-8510: frame size sha1-generic sha1-ssse3 delta 64 byte 37.5 MBit/s 37.5 MBit/s 0.0% 128 byte 56.3 MBit/s 62.5 MBit/s +11.0% 256 byte 87.5 MBit/s 100.0 MBit/s +14.3% 512 byte 131.3 MBit/s 150.0 MBit/s +14.2% 1024 byte 162.5 MBit/s 193.8 MBit/s +19.3% 1280 byte 175.0 MBit/s 212.5 MBit/s +21.4% 1420 byte 175.0 MBit/s 218.7 MBit/s +25.0% 1518 byte 150.0 MBit/s 181.2 MBit/s +20.8% The throughput for the largest frame size is lower than for the previous size because the IP packets need to be fragmented in this case to make there way through the IPsec tunnel. Signed-off-by: Mathias Krause <minipli@googlemail.com> Cc: Maxim Locktyukhin <maxim.locktyukhin@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
241 lines
5.8 KiB
C
241 lines
5.8 KiB
C
/*
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* Cryptographic API.
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*
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* Glue code for the SHA1 Secure Hash Algorithm assembler implementation using
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* Supplemental SSE3 instructions.
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*
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* This file is based on sha1_generic.c
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*
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* Copyright (c) Alan Smithee.
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* Copyright (c) Andrew McDonald <andrew@mcdonald.org.uk>
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* Copyright (c) Jean-Francois Dive <jef@linuxbe.org>
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* Copyright (c) Mathias Krause <minipli@googlemail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <crypto/internal/hash.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/mm.h>
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#include <linux/cryptohash.h>
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#include <linux/types.h>
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#include <crypto/sha.h>
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#include <asm/byteorder.h>
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#include <asm/i387.h>
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#include <asm/xcr.h>
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#include <asm/xsave.h>
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asmlinkage void sha1_transform_ssse3(u32 *digest, const char *data,
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unsigned int rounds);
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#ifdef SHA1_ENABLE_AVX_SUPPORT
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asmlinkage void sha1_transform_avx(u32 *digest, const char *data,
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unsigned int rounds);
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#endif
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static asmlinkage void (*sha1_transform_asm)(u32 *, const char *, unsigned int);
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static int sha1_ssse3_init(struct shash_desc *desc)
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{
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struct sha1_state *sctx = shash_desc_ctx(desc);
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*sctx = (struct sha1_state){
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.state = { SHA1_H0, SHA1_H1, SHA1_H2, SHA1_H3, SHA1_H4 },
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};
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return 0;
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}
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static int __sha1_ssse3_update(struct shash_desc *desc, const u8 *data,
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unsigned int len, unsigned int partial)
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{
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struct sha1_state *sctx = shash_desc_ctx(desc);
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unsigned int done = 0;
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sctx->count += len;
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if (partial) {
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done = SHA1_BLOCK_SIZE - partial;
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memcpy(sctx->buffer + partial, data, done);
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sha1_transform_asm(sctx->state, sctx->buffer, 1);
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}
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if (len - done >= SHA1_BLOCK_SIZE) {
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const unsigned int rounds = (len - done) / SHA1_BLOCK_SIZE;
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sha1_transform_asm(sctx->state, data + done, rounds);
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done += rounds * SHA1_BLOCK_SIZE;
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}
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memcpy(sctx->buffer, data + done, len - done);
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return 0;
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}
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static int sha1_ssse3_update(struct shash_desc *desc, const u8 *data,
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unsigned int len)
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{
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struct sha1_state *sctx = shash_desc_ctx(desc);
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unsigned int partial = sctx->count % SHA1_BLOCK_SIZE;
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int res;
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/* Handle the fast case right here */
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if (partial + len < SHA1_BLOCK_SIZE) {
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sctx->count += len;
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memcpy(sctx->buffer + partial, data, len);
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return 0;
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}
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if (!irq_fpu_usable()) {
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res = crypto_sha1_update(desc, data, len);
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} else {
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kernel_fpu_begin();
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res = __sha1_ssse3_update(desc, data, len, partial);
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kernel_fpu_end();
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}
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return res;
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}
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/* Add padding and return the message digest. */
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static int sha1_ssse3_final(struct shash_desc *desc, u8 *out)
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{
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struct sha1_state *sctx = shash_desc_ctx(desc);
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unsigned int i, index, padlen;
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__be32 *dst = (__be32 *)out;
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__be64 bits;
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static const u8 padding[SHA1_BLOCK_SIZE] = { 0x80, };
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bits = cpu_to_be64(sctx->count << 3);
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/* Pad out to 56 mod 64 and append length */
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index = sctx->count % SHA1_BLOCK_SIZE;
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padlen = (index < 56) ? (56 - index) : ((SHA1_BLOCK_SIZE+56) - index);
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if (!irq_fpu_usable()) {
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crypto_sha1_update(desc, padding, padlen);
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crypto_sha1_update(desc, (const u8 *)&bits, sizeof(bits));
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} else {
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kernel_fpu_begin();
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/* We need to fill a whole block for __sha1_ssse3_update() */
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if (padlen <= 56) {
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sctx->count += padlen;
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memcpy(sctx->buffer + index, padding, padlen);
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} else {
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__sha1_ssse3_update(desc, padding, padlen, index);
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}
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__sha1_ssse3_update(desc, (const u8 *)&bits, sizeof(bits), 56);
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kernel_fpu_end();
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}
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/* Store state in digest */
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for (i = 0; i < 5; i++)
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dst[i] = cpu_to_be32(sctx->state[i]);
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/* Wipe context */
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memset(sctx, 0, sizeof(*sctx));
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return 0;
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}
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static int sha1_ssse3_export(struct shash_desc *desc, void *out)
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{
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struct sha1_state *sctx = shash_desc_ctx(desc);
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memcpy(out, sctx, sizeof(*sctx));
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return 0;
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}
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static int sha1_ssse3_import(struct shash_desc *desc, const void *in)
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{
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struct sha1_state *sctx = shash_desc_ctx(desc);
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memcpy(sctx, in, sizeof(*sctx));
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return 0;
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}
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static struct shash_alg alg = {
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.digestsize = SHA1_DIGEST_SIZE,
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.init = sha1_ssse3_init,
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.update = sha1_ssse3_update,
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.final = sha1_ssse3_final,
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.export = sha1_ssse3_export,
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.import = sha1_ssse3_import,
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.descsize = sizeof(struct sha1_state),
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.statesize = sizeof(struct sha1_state),
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.base = {
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.cra_name = "sha1",
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.cra_driver_name= "sha1-ssse3",
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.cra_priority = 150,
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.cra_flags = CRYPTO_ALG_TYPE_SHASH,
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.cra_blocksize = SHA1_BLOCK_SIZE,
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.cra_module = THIS_MODULE,
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}
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};
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#ifdef SHA1_ENABLE_AVX_SUPPORT
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static bool __init avx_usable(void)
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{
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u64 xcr0;
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if (!cpu_has_avx || !cpu_has_osxsave)
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return false;
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xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
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if ((xcr0 & (XSTATE_SSE | XSTATE_YMM)) != (XSTATE_SSE | XSTATE_YMM)) {
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pr_info("AVX detected but unusable.\n");
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return false;
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}
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return true;
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}
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#endif
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static int __init sha1_ssse3_mod_init(void)
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{
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/* test for SSSE3 first */
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if (cpu_has_ssse3)
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sha1_transform_asm = sha1_transform_ssse3;
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#ifdef SHA1_ENABLE_AVX_SUPPORT
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/* allow AVX to override SSSE3, it's a little faster */
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if (avx_usable())
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sha1_transform_asm = sha1_transform_avx;
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#endif
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if (sha1_transform_asm) {
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pr_info("Using %s optimized SHA-1 implementation\n",
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sha1_transform_asm == sha1_transform_ssse3 ? "SSSE3"
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: "AVX");
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return crypto_register_shash(&alg);
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}
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pr_info("Neither AVX nor SSSE3 is available/usable.\n");
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return -ENODEV;
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}
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static void __exit sha1_ssse3_mod_fini(void)
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{
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crypto_unregister_shash(&alg);
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}
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module_init(sha1_ssse3_mod_init);
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module_exit(sha1_ssse3_mod_fini);
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("SHA1 Secure Hash Algorithm, Supplemental SSE3 accelerated");
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MODULE_ALIAS("sha1");
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